Hi,
I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"
we can see several information regarding a cache line. Those are:
1. Current data in cache
2. its 4-bit MOESI state,
3. Outer Memory Attribute
4. its tag
5. NS State.
However, there is no further elaboration regarding the encoding of MOESI state and
Outer Memory Attribute. Could anyone please elaborate these?
I saw the same documentation at Cortex-A53 and it shows some encoding of the state,
is it safe to assume the same encoding for Cortex-A7 too?
Thanks