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Hi,
I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"
we can see several information regarding a cache line. Those are:
1. Current data in cache
2. its 4-bit MOESI state,
3. Outer Memory Attribute
4. its tag
5. NS State.
However, there is no further elaboration regarding the encoding of MOESI state and
Outer Memory Attribute. Could anyone please elaborate these?
I saw the same documentation at Cortex-A53 and it shows some encoding of the state,
is it safe to assume the same encoding for Cortex-A7 too?
Thanks
isaansh wrote:Hi, I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"we can see several information regarding a cache line. Those are:1. Current data in cache2. its 4-bit MOESI state,3. Outer Memory Attribute4. its tag5. NS State.However, there is no further elaboration regarding the encoding of MOESI state andOuter Memory Attribute. Could anyone please elaborate these?
isaansh wrote:
Unfortunately not. ARM only provides this information to debug partners and silicon partners where they require that information.
DS-5 supports decoding the above information, from DS-5 5.25.0 onwards (for Cortex-A7) and earlier versions (for a few other cores like Cortex-A53, Cortex-A57, Cortex-A15). If you truly require introspection of cache contents then this is your best bet.
I saw the same documentation at Cortex-A53 and it shows some encoding of the state,is it safe to assume the same encoding for Cortex-A7 too? Thanks
Similarly, no. The format isn't the same.
Ta,
Matt