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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3586 Questions
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  • Answered

    GICv3: setting G1SEN / G1NSEN in GICD_CTLR 0

    • GICv3/v4
    5034 views
    3 replies
    Latest over 8 years ago
    by Vincent Siles
  • Answered

    is it possible to flush/invalidate cache from user space for AARCH32 0

    • Processors
    6708 views
    2 replies
    Latest over 8 years ago
    by yang
  • Answered

    AM3352 TrustZone +1

    • Mbed
    • am3352
    • TrustZone
    7511 views
    1 reply
    Latest over 8 years ago
    by Matthijs van Duin
  • Answered

    GIC-400 address layout in deviation from standard? +1

    4203 views
    2 replies
    Latest over 8 years ago
    by Matthias Welwarsky
  • Answered

    GIC-v3: control of group 0 interrupts activation and selection 0

    • GICv3/v4
    5680 views
    2 replies
    Latest over 8 years ago
    by Vincent Siles
  • Answered

    Can Cortex-A53 be used in lock-step mode? +1

    • Cortex-A53
    • Cortex-A
    5034 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    GIC-v3: optional asymetric / legacy support 0

    • GICv3/v4
    5059 views
    2 replies
    Latest over 8 years ago
    by Vincent Siles
  • Answered

    GICv3 and aarch32 0

    • GICv3/v4
    • AArch32
    5501 views
    2 replies
    Latest over 8 years ago
    by Vincent Siles
  • Answered

    ARMv8-M - toolchains / virtual platforms 0

    • Toolchain
    • Armv8
    • GCC
    • QEMU
    • Fast Models
    • TrustZone
    • Fixed Virtual Platforms (FVPs)
    • Armv8-M
    5371 views
    2 replies
    Latest over 8 years ago
    by Pierre
  • Answered

    Count the number of trailing zeros without clz? +1

    • Cortex-M0
    • Cortex-M
    • Arm Assembly Language (ASM)
    10487 views
    4 replies
    Latest over 8 years ago
    by Simon Craske Arm Employee Badge
  • Not Answered

    ASIMD multiply-accumulate instruction 0

    10673 views
    1 reply
    Latest over 8 years ago
    by venkataramanan
  • Answered

    how to get fastmodel license for cortex-A15 0

    • Cortex-A15
    • Fast Models
    9020 views
    3 replies
    Latest over 8 years ago
    by Martin K.
  • Not Answered

    pre emption of the interrupts in the cortex m3 arm v7 0

    • Cortex-M3
    8989 views
    3 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    How to know thumb code or arm code? +1

    12164 views
    6 replies
    Latest over 8 years ago
    by 박주병
  • Answered

    Why Cortex-R5 Bus-ECC documentation different from Cortex-R7 0

    5081 views
    3 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    why do we need two priviledged modes? cant one do the thing in cortex m3 +2

    • processor modes
    • Cortex-M3
    14756 views
    6 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    arm7tdmi APMC_CGMR PLL +1

    4268 views
    3 replies
    Latest over 8 years ago
    by G. Goodwin L. Pitos
  • Answered

    Flash/RAM memory interfaces on Cortex-M7 based MCU for fast code execution 0

    • Cortex-M7
    11931 views
    1 reply
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    how cortex m4 processor executing inst from a 'C' file +1

    5484 views
    4 replies
    Latest over 8 years ago
    by daith
  • Answered

    Is it possible at all to inspect DCACHE line bytes (and flags) on the Cortex-A9 core by reading/writing CP14 or (less likely CP15)? +1

    • Cortex-A9
    • Cortex-A
    2691 views
    1 reply
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
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  • Armv7-A
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