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INVPC Hard fault exception error

Note: This was originally posted on 16th July 2009 at http://forums.arm.com

Using and Arm Cortex M3, the application that is running sometimes will generate a hard fault and deciphering the CFSR register tells me that the following user fault is triggerred.

From the Cortex manual:INVPC - Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid
value. The return PC points to the instruction that tried to set the PC.


Not sure where to proceed as the PC is pointing to the line in the exception handler. I am trying to figure out the instruction that triggerred the hard fault. Anybody have any suggestions?
  • Note: This was originally posted on 16th July 2009 at http://forums.arm.com

    There are a number of possible reasons for this fault.  For example

    1) Invalid value in EXC_RETURN number during exception return.
    For example,
    "¢ Return to thread with EXC_RETURN = 0xFFFFFFF1
    "¢ Return to handler with EXC_RETURN = 0xFFFFFFF9
    To investigate the problem, the current LR value provides the value of LR at the failing exception return.

    2) Invalid exception active status. For example:
    "¢ Exception return with exception active bit for the current exception already cleared. Possibly caused by use of VECTCLRACTIVE, or clearing of exception active status in NVIC SHCSR.
    "¢ Exception return to thread with one (or more) exception active bit still active.

    3) Stack corruption causing the stacked IPSR to be incorrect.
    For INVPC fault, the Stacked PC shows the point where the faulting exception interrupted the main / preempted program. To investigate the cause of the problem, it is best to use exception trace feature in ITM.

    4) ICI/IT bit invalid for current instruction.  This can happen when a multiple-load/store instruction gets interrupted and, during the interrupt handler, the stacked PC is modified.  When the interrupt return takes place, the non-zero ICI bit is applied to an instruction that do not use ICI bits.  The same problem can also happen due to corruption of stacked PSR.

    regards,
    Joseph



    Thanks for the response

    My R4 register has an address for an intrinsic IAR function that is never called in my program. R4  is always at the same address at fault

    My LR is 0xFFFFFFFD. I think this means the following:

    Return to Thread mode.
    Exception return gets state from the process stack.
    On return execution uses the process stack.
  • Note: This was originally posted on 20th July 2009 at http://forums.arm.com

    It is hard to guess what went wrong from the limiting information.

    It would be useful to see the value of the stacked PSR, which might show which handler is the last executed ISR.
    Also you should check the SP values to see if they are in correct memory space.

    Could you clarify
    "The return PC points to the instruction that tried to set the PC. "
    What instruction is it? Is it a instruction withing exception handler?

    If you are using KEIL tool, there is a feature that allow exception trace via ULINK2.
    I don't know if there is similar feature in IAR tool.


    Here is copy of my registers from the debugger breaking inside the hard fault exception handler.
  • Note: This was originally posted on 21st July 2009 at http://forums.arm.com

    Just seeing the register values at the starting of hardfault handler is not enough.
    You also need to find out the register values that are pushed to the stack as
    it enter hardfault handler.

    The value of R4 might not mean anything.  The program could have gone wrong
    for a number of cycle before entering hard fault, and load this value as a literal
    data accidentally. I don't know about the IAR function __iar_Tls_dtor__Isdst_rules.
    Have you contact IAR support about this? They might be able to help.

    Have you try to find out if IAR tool got exception event trace?
    If not, define a couple of global variables that work as a shift register to record the last couple of exceptions.
    This might help locate the problem.

    Are you using really Process Stack?
    Another possible issue is that the Main Stack Pointer and the Process Stack Pointer values are quite close.
    Are you sure they haven't got overlapped by mistake?



    We are using FreeRtos and I increased the priority on the main process Task in my program and I have not been able to reproduce the hardfault since. Could this issue have been cause by resource-sharing conflict?
  • Note: This was originally posted on 16th July 2009 at http://forums.arm.com

    There are a number of possible reasons for this fault.  For example

    1) Invalid value in EXC_RETURN number during exception return.
    For example,
    "¢ Return to thread with EXC_RETURN = 0xFFFFFFF1
    "¢ Return to handler with EXC_RETURN = 0xFFFFFFF9
    To investigate the problem, the current LR value provides the value of LR at the failing exception return.

    2) Invalid exception active status. For example:
    "¢ Exception return with exception active bit for the current exception already cleared. Possibly caused by use of VECTCLRACTIVE, or clearing of exception active status in NVIC SHCSR.
    "¢ Exception return to thread with one (or more) exception active bit still active.

    3) Stack corruption causing the stacked IPSR to be incorrect.
    For INVPC fault, the Stacked PC shows the point where the faulting exception interrupted the main / preempted program. To investigate the cause of the problem, it is best to use exception trace feature in ITM.

    4) ICI/IT bit invalid for current instruction.  This can happen when a multiple-load/store instruction gets interrupted and, during the interrupt handler, the stacked PC is modified.  When the interrupt return takes place, the non-zero ICI bit is applied to an instruction that do not use ICI bits.  The same problem can also happen due to corruption of stacked PSR.

    regards,
    Joseph
  • Note: This was originally posted on 17th July 2009 at http://forums.arm.com

    It is hard to guess what went wrong from the limiting information.

    It would be useful to see the value of the stacked PSR, which might show which handler is the last executed ISR.
    Also you should check the SP values to see if they are in correct memory space.

    Could you clarify
    "The return PC points to the instruction that tried to set the PC. "
    What instruction is it? Is it a instruction withing exception handler?

    If you are using KEIL tool, there is a feature that allow exception trace via ULINK2.
    I don't know if there is similar feature in IAR tool.
  • Note: This was originally posted on 20th July 2009 at http://forums.arm.com

    Just seeing the register values at the starting of hardfault handler is not enough.
    You also need to find out the register values that are pushed to the stack as
    it enter hardfault handler.

    The value of R4 might not mean anything.  The program could have gone wrong
    for a number of cycle before entering hard fault, and load this value as a literal
    data accidentally. I don't know about the IAR function __iar_Tls_dtor__Isdst_rules.
    Have you contact IAR support about this? They might be able to help.

    Have you try to find out if IAR tool got exception event trace?
    If not, define a couple of global variables that work as a shift register to record the last couple of exceptions.
    This might help locate the problem.

    Are you using really Process Stack?
    Another possible issue is that the Main Stack Pointer and the Process Stack Pointer values are quite close.
    Are you sure they haven't got overlapped by mistake?
  • Note: This was originally posted on 22nd July 2009 at http://forums.arm.com

    I don't know. Have you try contact FreeRTOS for support?
  • Hi,
    I encountered the same problem.
    It turned out to be a recursive call.