Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    Non-secure call Secure used SG instruction cause Hard Fault 0

    3377 views
    6 replies
    Latest over 3 years ago
    by Thomas Coding
  • Suggested Answer

    Conditional Non-branch Instructions 0

    • ETM
    1993 views
    2 replies
    Latest over 3 years ago
    by Willy Wolff Arm Employee Badge
  • Not Answered

    How high is the precision of fixed-point processors for floating-point numbers? 0

    • Processors
    1431 views
    1 reply
    Latest over 3 years ago
    by 42Bastian Schick
  • Not Answered

    Failed to Generate Application Project in Vitis 2020.1 for Cortex M1 softcore processor on Arty A7 100T FPGA. 0

    • FPGA Xilinx
    • Cortex-M1
    • FPGA
    3289 views
    0 replies
    Started over 3 years ago
    by Vybhav MN
  • Answered

    How to read/write an I/O port in aarch64? 0

    • AArch64
    • Arm64
    7196 views
    3 replies
    Latest over 3 years ago
    by LucasBarros90
  • Not Answered

    Multiple ARM CPU in the same Motherboard 0

    3508 views
    2 replies
    Latest over 3 years ago
    by sidereal
  • Answered

    How to compute a cache size? +1

    8784 views
    2 replies
    Latest over 3 years ago
    by ted
  • Suggested Answer

    What's the meaning of the entry of exception vector for ARM-VA7 0

    • Armv7-A
    2794 views
    4 replies
    Latest over 3 years ago
    by asic_xuan
  • Not Answered

    the halt of Systick 0

    • CoreSight Architecture
    • 15 (SysTick)
    1751 views
    2 replies
    Latest over 3 years ago
    by asic_xuan
  • Not Answered

    Cortex M33 Return to Non Secure Thread from Secure SVC 0

    • TrustZone for Armv8-M
    • Cortex-M33
    2071 views
    0 replies
    Started over 3 years ago
    by mcak
  • Not Answered

    How do we correctly use the CMSIS-DSP functions that have fixed-point (Qx) input/outputs? 0

    • Digital Signal Processor (DSP)
    • CMSIS
    2587 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Answered

    Initialization an array of 24-bit signed integers 0

    • Cortex-M3
    • Arm Assembly Language (ASM)
    3197 views
    5 replies
    Latest over 3 years ago
    by WestfW
  • Not Answered

    Setting Non-Secure Memory from Secure Memory on TrustZone for Armv8-m 0

    • TrustZone for Armv8-M
    • Cortex-M33
    3385 views
    4 replies
    Latest over 3 years ago
    by mcak
  • Answered

    Wrong interrupt vector called 0

    • Interrupt Handling
    • Interrupt Controllers
    • Cortex-M4
    4345 views
    10 replies
    Latest over 3 years ago
    by Stric
  • Answered

    Very Urgent :VIC in ARM Cortex R4 +1

    • Cortex-R
    • Cortex-R4
    12259 views
    14 replies
    Latest over 3 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    How can I build ATF opteed in aarch32 EL3 runtime software(BL32)? 0

    • Arm Trusted Firmware
    • Armv7-A
    • Armv8-A
    • TrustZone
    3420 views
    2 replies
    Latest over 3 years ago
    by Emmy0
  • Answered

    Cortex-A15 Cache Maintenance DCIMVAC vs DCCIMVAC 0

    • Cortex-A15
    • Cache Management
    3689 views
    3 replies
    Latest over 3 years ago
    by Dylan1234
  • Not Answered

    complex signals 0

    1322 views
    1 reply
    Latest over 3 years ago
    by 42Bastian Schick
  • Answered

    Cycle counter: on which ARM will the code successfully run? 0

    • Cortex-A53
    • Armv7-A
    • Raspberry Pi 3
    • Architectures
    3541 views
    6 replies
    Latest over 3 years ago
    by 42Bastian Schick
  • Not Answered

    Error: unknown mnemonic `mcr' for aarch64? 0

    • AArch64
    • AArch32
    6854 views
    2 replies
    Latest over 3 years ago
    by vstehle Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone