On a Raspberry Pi 3b, which is ARM Cortex-A5 processor, ARMv7 architecture, I am reading the cycle counter registers from the PMU (Performance Monitor Unit):
uint32_t cycle_counter_read (void){ uint32_t cc = 0; __asm__ volatile ("mrc p15, 0, %0, c9, c13, 0":"=r" (cc)); return cc;}
uint32_t cycle_counter_read (void)
{
uint32_t cc = 0;
__asm__ volatile ("mrc p15, 0, %0, c9, c13, 0":"=r" (cc));
return cc;
}
I'd like to understand on which ARM processors will this code run successfully, other than the one in Raspberry Pi 3B.
Which ARM info is important for this:
Currently I have included this code only for ARMv7:
#if defined(PLATFORM_ARMV7)
cycle_counter_read();
#endif
Thanks.
Hi Former Member,
Note that RaspberryPi 3B has a 64b Armv8 Cortex-A53 CPU (more details here). It seems you might be running in 32b AArch32 mode, as is the case under RaspberryPi OS.
The PMCCNTR register you are reading is fairly common. Quoting the architecture manuals:
- It is present on Armv7-A/R CPUs implementing the Performance Monitors Extension.
- It is also present on Armv8-A CPUs supporting AArch32 at EL0 and implementing FEAT_PMUv3 (in which case it corresponds to the low part of the AArch64 PMCCNTR_EL0 register).
Best regards,
Vincent.
Other architectures have a cycle counter in a different place. in ARMv7m, for example, there is DWT->CYCCNT in the Debug, Watchpoint, and Trace unit.
Still not sure which platforms other than armv7 will understand __asm__ volatile ("mrc p15, 0, %0, c9, c13, 0":"=r" (cc));
nor how do I check if the platform understands it.
Simply by checking the respective architecture manuals!
If your code is for Linux, you need to check Armv7-A, Armv8-A and Armv9-A.
I was hoping there is some other way, but it's good to know that R T F Manual is all there is to it.
Afaik there are registers that you can check at runtime if a special functionality is supported. So you can check if the PMU exists, but not the opcodes you need to access it.