I am trying to understand the difference between the DCIMVAC and DCCIMVAC cache maintenance operations in the Cortex-A15 architecture. I have run some tests on a TI AM5718 SOC that features a single-core Cortex-A15 MPCore (revision r2p2), and it appears that the DCIMVAC operation cleans the cache line (if it is dirty) out to main memory prior to invalidating it. I am trying to understand if this expected behavior or I have something configured incorrectly. Does the Cortex-A15 have a cache maintenance instruction that is guaranteed to only invalidate without cleaning?From the ARM Cortex-A15 MPCore Processor Technical Reference Manual:
Then looking at the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition:
Both of these documents seem to suggest that DCIMVAC will only invalidate, and DCCIMVAC will clean and invalidate, however, in my experiments, DCIMVAC seems to clean the cache line, if dirty, as well as invalidate it. I was able to find one document that made me think this could be expected behavior. In the Cortex-A15 MPCore - NEON Software Developers Errata Notice errata item 794724 includes the following statement: "The DCISW invalidate by set/way instruction is treated by A15 as a DCCISW clean/invalidate by set/way instruction." This statement isn't part of the errata description, but rather stated as a given in the workaround explanation. This is curious, because the behavior of DCISW being treated as DCCISW, seems similar to what I am experiencing with DCIMVAC being treated as DCCIMVAC, and neither behavior seems to be documented in the ARM Cortex-A15 MPCore Processor Technical Reference Manual.Excerpt from errata 794724:
Interestingly, I see that the ARM Cortex-A53 MPCore Processor Technical Reference Manual does include verbiage about this behavior. It states "DCIMVAC operations in AArch32 and DCIVAC instructions in AArch64 perform an invalidate of the target address. If the data is dirty in the executing core then a clean is performed before the invalidate.
Given that this behavior seemed worth documenting specifically in the A53 manual, I am surprised to see it missing from the A15 manual. The behavior of DCIMVAC acting like DCCIMVAC isn't problematic, I'm just concerned that I am misunderstanding something, since the experimental behavior didn't seem to be what I expected from reading the documentation. Can it be verified that DCIMVAC will always clean on Cortex-A15, or is this a behavior that could be specific to the TI chip I am working with?
I found a discussion about this from TI's forums talk about a different A15 SOC https://e2e.ti.com/support/processors-group/processors/f/processors-forum/544363/does-the-arm-cortex-a15-treat-the-invalidate-instruction-as-a-clean-invalidate-instruction-due-to-a-design-decision-or-due-to-an-errata Ultimately, however, I am still not clear if the behavior is expected or not.
Cortex-A7 manual has a comment about the upgradation of DCIMVAC to DCCIMVAC.
It seems that AM5718 has virtualization extensions available. The armv7-a-r manual notes: "Functionally, upgrading DCIMVAC to DCCIMVAC is acceptable for any data invalidate by MVA executed in a Non-secure PL1 mode. Therefore, the implementation documentation might not specify the exact conditions in which this upgrade occurs."
Thank you! This is exactly what I was looking for.