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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    The BBC Micro:bit - 2 totally different computers... how convenient 0

    • Cortex-M0
    • Input/Output Cells
    • BBC micro:bit
    • PrimeCell General Purpose Input/Output (PL061)
    • audio
    • Arm Assembly Language (ASM)
    • Cortex-M4
    3506 views
    2 replies
    Latest over 3 years ago
    by WestfW
  • Not Answered

    Cortex M55 Trustzone recommendations before jumping to next level software 0

    1194 views
    0 replies
    Started over 3 years ago
    by TexCorJC
  • Suggested Answer

    AXI4 Narrow and possibly unaligned READ 0

    5004 views
    4 replies
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Cortex-M23: Dumping values on the stack 0

    2489 views
    1 reply
    Latest over 3 years ago
    by 42Bastian Schick
  • Answered

    Can HTRANS change from IDLE to NONSEQ during AHB error response? 0

    • AHB-Lite
    • AHB5
    2237 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    For a same virtual address, does the secure EL1/0 and non-secure EL1/0 see the same physical address? 0

    • secure systems
    • Armv8-A
    • Memory Management Unit (MMU)
    2388 views
    2 replies
    Latest over 3 years ago
    by asic_xuan
  • Answered

    Are there any GIC500 API? 0

    • GICv3/v4
    1589 views
    2 replies
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Is the bare-metal boot code for A53 also usable for A35? 0

    2715 views
    4 replies
    Latest over 3 years ago
    by asic_xuan
  • Answered

    DIC/IDC bit in CTR +1

    4547 views
    6 replies
    Latest over 3 years ago
    by a.surati
  • Answered

    ICPR usage in Arm Cortex m4 +1

    • Cortex-M4
    2577 views
    2 replies
    Latest over 3 years ago
    by Yorker Hazan
  • Not Answered

    How does the 4x4 Matrix Key Board on the microcontroller work 0

    1462 views
    2 replies
    Latest over 3 years ago
    by 42Bastian Schick
  • Answered

    When will be the Release of "The Definitive Guide to Cortex M7" ?? 0

    • Cortex-M7
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    8626 views
    4 replies
    Latest over 3 years ago
    by Adam G.
  • Not Answered

    CoreSight Components Technical Reference Manual (Assembly code for Stimulus Registers) 0

    • CoreSight Debug and Trace
    2329 views
    0 replies
    Started over 3 years ago
    by adrianmn
  • Not Answered

    Founder looking at custom SoC to reduce BOM costs 0

    1144 views
    0 replies
    Started over 3 years ago
    by Danny P
  • Not Answered

    Cortex-A53 L2 cache invalidation 0

    • Cortex-A53
    • Cache Management
    • Cache Architecture
    2927 views
    2 replies
    Latest over 3 years ago
    by Kalex
  • Not Answered

    M7 atomic operation faults on non cacheable memory 0

    • 5 (BusFault)
    • STM32 F7
    6722 views
    8 replies
    Latest over 3 years ago
    by Clay McClure
  • Not Answered

    Having trouble with interrupt latency and cycle time in M0+ 0

    • Interrupt Handling
    • Clocking Structures & Timing Mechanisms
    • Cortex-M0+
    1122 views
    0 replies
    Started over 3 years ago
    by KhanZ
  • Not Answered

    GICv2 Interrupt auto deassertion - Cortex-R5 0

    • GICv2
    • Cortex-R5
    1199 views
    0 replies
    Started over 3 years ago
    by ijahmad
  • Not Answered

    How does Realm VM deal with interrupts? 0

    1309 views
    0 replies
    Started over 3 years ago
    by echov8
  • Suggested Answer

    Cortex A53 and AMP Asynchronous Multiprocessing 0

    • Cache coherency
    • Cache Coherent Interconnect
    • Cortex-A
    4881 views
    5 replies
    Latest over 3 years ago
    by 42Bastian Schick
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