Is it possible to invalidate by software the L2 cache in Cortex-A53?
My code is currently too small to produce cache misses in the L2 cache so that I would like to simulate L2 cache misses by invalidating the L2 cache to be able check the performance degradation.
If yes, how to do it? Is "ic ialluis" + "isb sy" the correct way to do it?
AFAIK there is no way to flush/invalidate the L2 Cache Independently.
Thank you. Do you mean that if L1 cache (data or instruction? or both?) is invalidated, then L2 cache is also invalidated? Or do you mean that if L1 cache is invalidated, then L2 cache stays unchanged and there is no possibility to invalidate it?