I am using an SOC with GIC (probably v2) on Cortex-R. I have timer interrupt at IRQ#226. I have enabled it in distributor block and cpu block in Group#1.
The moment I enable the interrupt it is asserted as shown in figure below (as its in pending state). The interrupt appears in acknowledge register.
but when in step over to next instructions, the interrupt is deasserted and also CPU doesn't receives the interrupt. The sudden change of Acknowledge register value is shown in figure below.
Please give me a clue here!