ICPR usage in Arm Cortex m4

Hi all,

I am trying to understand fully how does interrupt handling works in Arm cortex m4 systems.

Correct me if im mistaken but the flow is that an IRQ is set pending using the ISPR and cleared from pending using the ICPR register.

I understand that the IRQ is set pending by NVIC.

Something that is unclear to me is who is responsible of clearing pending interrupts using ICPR?

Is it the responsibility of NVIC or of the ISR?

The reference manual specifies the usage of the ICPR but not who should use it.

Any help would be greatly appreciated.

Thank you.