Hi all,
I am trying to understand fully how does interrupt handling works in Arm cortex m4 systems.
Correct me if im mistaken but the flow is that an IRQ is set pending using the ISPR and cleared from pending using the ICPR register.
I understand that the IRQ is set pending by NVIC.
Something that is unclear to me is who is responsible of clearing pending interrupts using ICPR?
Is it the responsibility of NVIC or of the ISR?
The reference manual specifies the usage of the ICPR but not who should use it.
Any help would be greatly appreciated.
Thank you.
NVIC clears the PENDING status (and sets the ACTIVE status) of the interrupt when the CPU begins servicing it. So, the PENDING status is automatically cleared by the NVIC.
It may also happen that while the CPU is servicing the interrupt (i.e. the interrupt is ACTIVE), another instance of the same interrupt may arise. Then, it is sampled and made PENDING by the NVIC. Thus the interrupt is both ACTIVE on the CPU, and PENDING in the NVIC. When the interrupt handler returns, the NVIC will signal the same interrupt again to the CPU (since another instance is PENDING). But the handler, when servicing the first instance, may decide that its work is done sufficiently well so that any other instance of the same interrupt, which may have arrived while the handler was servicing the first instance, can be ignored. In that case, the handler can turn off the PENDING state by writing to the ICPR before returning.
ISPR/ICPR are meant for manually setting/clearing the PENDING state of an interrupt in the NVIC. The ICPR is useful in clearing any residual PENDING state of an interrupt before it is enabled, or after it is disabled.
Your example made it quite clear.
Thank you very much.