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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    Loading Bootloader from Flash to RAM +1

    14726 views
    5 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Statistical signal processing of radar signals 0

    1770 views
    0 replies
    Started over 6 years ago
    by shah87
  • Answered

    Capturing video on ARM Cortex M7 +1

    • Cortex-M7
    • Video Compression Standard
    6276 views
    6 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Pipeline Stages in the Cortex-A53 +1

    19430 views
    2 replies
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Answered

    NVIC and ARM asm +1

    • APB
    • Address
    • GPIO
    • Cortex-M3
    • Thumb
    • Class
    • DATE
    • Cortex-M
    • Arm Assembly Language (ASM)
    • GNU
    • Interrupt
    9688 views
    9 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    r0 corruption while making subroutine call on Cortex A-9 +1

    • Cortex-A9
    • Registers
    • R0
    13369 views
    8 replies
    Latest over 6 years ago
    by Vanhealsing
  • Not Answered

    Are 48-core ARM processors compatible with AMD RADEON and NVIDIA video cards? 0

    22419 views
    9 replies
    Latest over 6 years ago
    by look
  • Not Answered

    L2C-310 Cache Sync 0

    • CoreLink L2C-310 Level 2 Cache Controller
    9204 views
    0 replies
    Started over 6 years ago
    by christoph8446
  • Suggested Answer

    IT CPZ CPNZ 0

    • Thumb
    10195 views
    2 replies
    Latest over 6 years ago
    by Sean Dunlevy
  • Not Answered

    L2C-310 double linefill issuing 0

    • CoreLink L2C-310 Level 2 Cache Controller
    8468 views
    0 replies
    Started over 6 years ago
    by christoph8446
  • Answered

    Use GICv3 legacy support 0

    • GICv2
    • GICv3/v4
    12762 views
    4 replies
    Latest over 6 years ago
    by josecm
  • Suggested Answer

    ARMv7-a MPU/PMSA - Unified Region (Base/Size) question 0

    • Armv7-A
    • Memory Controller Devices
    • Memory Management Unit (MMU)
    • Memory Architecture
    • Memory Management
    • Memory
    9835 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    AHB5 did'nt mention SPLIT and RETRY responses 0

    • AHB5
    10741 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Trace decompressor: Are barrier instructions and synchronization primitives really waypoints? +1

    • Trace
    • CoreSight Debug and Trace
    • CoreSight PTM-A9
    9569 views
    2 replies
    Latest over 6 years ago
    by Oddjob6
  • Suggested Answer

    Fundamental Doubt in AHB Bus Architecture 0

    • Protocols
    • SoC Implementation
    • Interface Bus Architecture
    • Microcontroller (MCU)
    • Networking Protocol
    • AHB-Lite
    9913 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    What is meant by a Master in the AHB-Lite specification? 0

    12000 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    How to select endianess in AHB? +1

    10072 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Number of byte count 0

    9694 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Help with porting Intel AVX to arm64 +1

    • AArch64
    • Arm64
    16444 views
    1 reply
    Latest over 6 years ago
    by jtzhou
  • Answered

    MMU - Permission Fault with EL1 access +1

    • Cortex-A53
    • AArch64
    • Raspberry Pi 3
    • Armv8-A
    • Memory Management Unit (MMU)
    16120 views
    3 replies
    Latest over 6 years ago
    by Dumitru
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Topics being discussed in this forum
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