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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Not Answered

    Does ARM have a time counter mechanism? 0

    • Armv8-A
    • Cortex-A
    5795 views
    3 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    AD converter 0

    • Arm7
    • Arm7TDMI-S
    • Interrupt
    4615 views
    2 replies
    Latest over 10 years ago
    by Bojana
  • Answered

    Why the address width of MMU-500 is different with Cortex-A53/57? 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    10165 views
    4 replies
    Latest over 10 years ago
    by wangyong
  • Answered

    Regarding mismatched memory attributes and cacheability 0

    • Cortex-A9
    • Cache
    • Cortex-A
    11233 views
    7 replies
    Latest over 10 years ago
    by Matthijs van Duin
  • Not Answered

    Barrier Transactions - ACE Protocol 0

    • AMBA 4
    • ACE
    8894 views
    9 replies
    Latest over 10 years ago
    by LAKSHMI KANTH
  • Answered

    ARM Cotex-M0 memory allocation for structure array with bitfeilds +1

    • Cortex-M0
    • Cortex-M
    • Memory
    3340 views
    1 reply
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Im using an ARM Cortex-M3(LPC1768).I would like to know how many oscillator periods make up 1 instruction cycle for arm.Like for example,12 oscillator periods make up 1 instruction cycle for 8051. +1

    • Cortex-M3
    • Cortex-M
    9040 views
    5 replies
    Latest over 10 years ago
    by daith
  • Answered

    How to use the amba bus? 0

    • AMBA
    • Cortex-A9
    • Cortex-A
    8064 views
    4 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Cortex-M4 documentation 0

    • Cortex-M
    • Cortex-M4
    4636 views
    3 replies
    Latest over 10 years ago
    by Alban Rampon
  • Answered

    Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2? 0

    • Armv7-A
    • Cortex-A9
    • Cache
    • Cortex-A
    8180 views
    6 replies
    Latest over 10 years ago
    by Hemant
  • Answered

    I NEED INFO ABOUT THE ARM CORTEX-A9 ASAP!! +1

    • Cortex-A9
    • Cortex-A
    3954 views
    1 reply
    Latest over 10 years ago
    by Brad Nemire Arm Employee Badge
  • Answered

    Is there any available data about the PPA comparison b/w Cortex-A7 and Cortex-A53 +1

    • Cortex-A53
    • Cortex-A
    • Cortex-A7
    6406 views
    1 reply
    Latest over 10 years ago
    by Tom Stevens
  • Answered

    Interrupt on Out-of-Order pipeline of Cortex-A15 +1

    • Cortex-A15
    • Out-of-order Execution
    • Cortex-A
    • Interrupt
    7710 views
    5 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    behavior of executing instructions on the out-of-order pipeline of Cortex-A15 0

    • Cortex-A15
    • Out-of-order Execution
    • Cortex-A
    5121 views
    1 reply
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Compability between architecture ARMv5TE and ARMv7-A +1

    • Architecture
    • Armv7-A
    • Armv5TE
    11361 views
    1 reply
    Latest over 10 years ago
    by Mark Nicholson Arm Employee Badge
  • Answered

    Compacting 4x 24 bit values into 3x 32 bits 0

    • Cortex-M3
    • GNU Assembler
    • GCC
    9090 views
    6 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    How many ways to set a register 32 bit value? 0

    • 32-bit
    • Arm Assembly Language (ASM)
    22125 views
    2 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Unknown instruction jump +1

    • Cortex-A8
    • Processors
    4569 views
    1 reply
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Exception / Interrupt for Cortex-A15 0

    • Cortex-A15
    • Cortex-A
    • Interrupt
    4663 views
    2 replies
    Latest over 10 years ago
    by Michihiro Yamamoto
  • Answered

    Question about ARM exception and CPSR status +1

    • CPSR
    4697 views
    2 replies
    Latest over 10 years ago
    by daith
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Topics being discussed in this forum
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