HI,
Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?
Does it need to respond 16th? or we can respond 1 only?
Regards,
-GARO
Hi Garo,
an AXI master should distinguish an error with even one error response cycle.
Best regards,Yasuhiko Koumoto.
Hi Koumoto-san,
Thank you for your response.
In the AXI specification, does an AXI slave must be the response of the same number of times as the Length（AxLEN+1) to their master if the access was DECERR?
I think, if AXI specification have like an early response mode*, an AXI slave can respond only once for error access case even if length is not zero in their payload.
Cortex-A9 supports an "early BRESP", but it is out of AXI specification and it needs to control user bit[8].
However, our AXI slave doesn't use any user signals.
-Garo
as you say, the early is not AXI compliant. However I must correct myself a little. My answer of yesterday was valid for a read responce. As for a write response the BRESP values should be the same in a burst transaction according to the "AMBA® AXI™ and ACE™ Protocol Specification (ARM IHI 0022D (ID102711))".
A3.4.4 Read and write response structure
For a write transaction, a single response is signaled for the entire burst, and not for each data transfer within the burst.
In a read transaction, the slave can signal different responses for different transfers in a burst. For example, in a burst of 16 read transfers the slave might return an OKAY response for 15 of the transfers and a SLVERR response for one of the transfers.
The followings are my comments.An AXI master can check only the BRESP of the last responce for a write.Regarding the early BRESP, you can ignore AWUSER[8] and can return write responces as normally. AWUSER[8] only indicates the master can accept the early BRESP.
Thank you so much.
Let me check the document.
My slave has been response only once when it was operating both DECERR and SLVERR.
-write : My slave didn't check for enough asserted "WVALID" cycles, and it asserted BVALID before AXI master asserted WLAST.
-read : My slave asserted both RLAST and RVALID at next cycle of asserted RREADY.
I should re-design my AXI slave I/F.