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Hi Experts,
ARMv8 MMU TTBRn_ELx registers are banked by exception level.
In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1
and Non-secure EL1&0 stage 1 controlling register is also TTBR0_EL1.
Is same register TTBR0_EL1 between secure EL1 and non-secure EL1?
ARMv7 TTBR0 register is banked by secure/non-secure.
If program switches to secureos(secure world) from linux kernel(normal world), the MMU table is changed automatically.
How does ARMv8 MMU table work if program enter secure EL1 from non-secure EL1?
Thanks for your attention!
TTBR0_EL1 is the same register in secure EL1 and non-secure EL1 (if they are both AArch64.)
yan.wy wrote: If program switches to secureos(secure world) from linux kernel(normal world), the MMU table is changed automatically. How does ARMv8 MMU table work if program enter secure EL1 from non-secure EL1?
yan.wy wrote:
It is not possible to go directly from NS-EL1 to S_EL1, you must first go to EL3 (which is always secure.) The code running at EL3, usually called a secure monitor, will change the value in TTBR0_EL1 to the correct one for the target EL1.