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Architectures and Processors forum Reason for having decouple write address, data channels in AXI4

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Reason for having decouple write address, data channels in AXI4

Naveen over 10 years ago

Can someone explain me the advantage of having decouple write address, data channels in AXI4?

In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled write address, data channels will help?

Thanks

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Peter Harris over 10 years ago in reply to Naveen +1 verified

I believe that it is simply a form of pipelining - many memory technologies require some setup time after receiving an address before you can do anything useful with data (set up a row buffer in DDR, set...