how to understand ARMv8 exception level1 secure/non-secure MMU?

Hi Experts,

     ARMv8 MMU TTBRn_ELx registers are banked by exception level.

     In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1

     and Non-secure EL1&0 stage 1 controlling register is also TTBR0_EL1.    

     Is same register TTBR0_EL1 between secure EL1 and non-secure EL1?

     ARMv7 TTBR0 register is banked by secure/non-secure.

     If program switches to secureos(secure world) from linux kernel(normal world), the MMU table is changed automatically.

     How does ARMv8 MMU table work if program enter secure EL1 from non-secure EL1?

     Thanks for your attention!