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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3594 Questions
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  • Answered

    Cortex-A5 based processors +1

    • Cortex-A9
    • Cortex-A5
    • Cortex-A
    • Cortex-A8
    7237 views
    3 replies
    Latest over 10 years ago
    by Axel Heider
  • Not Answered

    ARM_V8 instruction Cycles timings 0

    • Cortex-A57
    • NEON
    • Cortex-A
    14006 views
    5 replies
    Latest over 10 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Compute the division via shift instruction +1

    • Cortex-M0
    • Cortex-M
    4104 views
    4 replies
    Latest over 10 years ago
    by Jerome Decamps - ćťśĺ°šćť°
  • Not Answered

    does different arm TRM revisions also have changes in Hardware? 0

    • Cortex-A9
    • Cortex-A
    3312 views
    2 replies
    Latest over 10 years ago
    by anoop
  • Answered

    ARM FULL VIRTUALISATION SOFTWARE 0

    • Cortex-A17
    • Cortex-A
    8739 views
    7 replies
    Latest over 10 years ago
    by Mike Clark
  • Answered

    ARM Cortex-M0 Details +1

    • Cortex-M0
    • Cortex-M
    17631 views
    7 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Not Answered

    TRANSFER CONTINUE AFTER ERROR RESPONSE FROM SLAVE 0

    • AMBA
    • AHB
    8074 views
    6 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    About PL310 cache controller and data aborts 0

    • Armv7-A
    • Cache
    4600 views
    2 replies
    Latest over 10 years ago
    by Niranjan Dighe
  • Answered

    I cannot write the sp register in the monitor mode +1

    • Armv7-A
    • Cortex-A
    • Cortex-A7
    24693 views
    21 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS. 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    6588 views
    3 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Cortex-A9/GIC: de-activate an active interrupt 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    5397 views
    2 replies
    Latest over 10 years ago
    by 42Bastian
  • Answered

    Issue about Cortex-A9 Dhrystone performance 0

    • Cortex-A9
    • Cortex-A
    15815 views
    12 replies
    Latest over 10 years ago
    by anoop
  • Answered

    MRS/MSR (Banked register) 0

    • Armv7-A
    • Armv7-R
    • Cortex-A
    • Cortex-A7
    8282 views
    4 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    Cortex-A72 and Cortex-A5x series boards 0

    • Cortex-A72
    • Cortex-A53
    • Cortex-A57
    • Cortex-A
    9415 views
    4 replies
    Latest over 10 years ago
    by techguyz
  • Answered

    Problem with storing data instruction STR (ASM) 0

    • Cortex-M
    35649 views
    16 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    What are hints? 0

    • Armv7-A
    • Armv7-R
    6200 views
    3 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    What will be happened if I insert a store instruction behind a LDREX instruction for accessing the same address? 0

    • Armv8-A
    • Armv8-R
    3004 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How to run an ARM 32bit binary on Juno Board in Linux and Android ? 0

    • Cortex-A9
    • Cortex-A
    • Linux
    6327 views
    4 replies
    Latest over 10 years ago
    by Mingting
  • Not Answered

    system requirements 0

    • Armv7-A
    • Cortex-M7
    • Armv7-M
    • Cortex-A
    • Cortex-A7
    • Cortex-M
    3186 views
    2 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    The merit of data cache cleaning +1

    • Armv7-A
    • Cortex-A9
    • Cache
    • Cortex-A
    8449 views
    5 replies
    Latest over 10 years ago
    by Henry Choi
<>
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