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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Not Answered

    Intercore interrupts on a53 between EL1 and EL3 0

    • Cortex-A53
    • Cortex-A
    5935 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Cache Allocation Technology 0

    • AArch64
    • Cache
    • Cortex-A
    • Cortex-A8
    • AArch32
    7074 views
    2 replies
    Latest over 8 years ago
    by daith
  • Answered

    how pc is updated during execution of SWI and any simple instruction like mov R1,R15? +1

    • R15 (PC Program Counter)
    • Armv4T
    • Arm7
    • R14 (LR Link Register)
    • Arm Assembly Language (ASM)
    11856 views
    8 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Suggested Answer

    ARM Cortex A8 L2 Cache Flush Invalidate 0

    • Cortex-A
    • Cortex-A8
    10018 views
    5 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Excepted Practice for NS writes after setting M33 SAU.ALLNS 0

    • TrustZone
    • Armv8-M
    • Block
    7126 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Help Choosing a processor +1

    • Cortex-M7
    • Cortex-M
    • Armv8-M
    • C
    2999 views
    1 reply
    Latest over 8 years ago
    by daith
  • Answered

    ABS (absolute value) function +1

    • SIMD and Vector Execution
    6913 views
    1 reply
    Latest over 8 years ago
    by daith
  • Answered

    What does system memory work actually? 0

    • CMSDK
    • Cortex-M
    4976 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    two’s complement 0

    • Armv7-M
    9382 views
    4 replies
    Latest over 8 years ago
    by thewal
  • Answered

    When does ITAdvance() pseudo-function Exactly called ? 0

    • T32 (Thumb)
    3578 views
    2 replies
    Latest over 8 years ago
    by AbdAllah Talaat
  • Not Answered

    L2 cache with cortex-A8 0

    • Cache
    • Cortex-A
    • Cortex-A8
    3342 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Suggested Answer

    Problem with SWO when debugger not connected 0

    • Cortex-M
    • Cortex-M4
    4480 views
    1 reply
    Latest over 8 years ago
    by ciaranmac
  • Answered

    ARMv7-M: Question about syn/asynchronous exception? 0

    • Armv7 Exception Model
    • Armv7-M
    5202 views
    4 replies
    Latest over 8 years ago
    by yenWu
  • Answered

    Arm Instruction Set (Thumb-2) +1

    • Cortex-M3
    • T32 (Thumb)
    • Cortex-M
    8084 views
    5 replies
    Latest over 8 years ago
    by AbdAllah Talaat
  • Answered

    How to use CoreSight debug and trace ? +1

    • Arm Development Studio
    • CoreSight Debug and Trace
    • Arm9
    6271 views
    1 reply
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    How to convert a BIN into an ELF object image with armlink? +1

    • Toolchain
    • Compilers
    • GNU Arm
    • Linux
    7372 views
    1 reply
    Latest over 8 years ago
    by Ed Player Arm Employee Badge
  • Answered

    A8: Keeping Cache-enabled and MMU-disabled +1

    • Cortex-A
    • Cortex-A8
    13414 views
    6 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Using an external clock - experts only +1

    • Raspberry Pi
    • Cortex-A53
    • Cortex-A57
    • Cortex-A
    9691 views
    5 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Not Answered

    ARMv7 CortexA9 Cache Policy - No allocate ? 0

    • Armv7-A
    • Cortex-A9
    • Cache
    • Cortex-A
    3136 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    CM4: Is DAP immune to MPU protections? +1

    • Cortex-M
    • Cortex-M4
    2402 views
    1 reply
    Latest over 8 years ago
    by 42Bastian Schick
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