Hi guys,
I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process to access?
As far as I know there is nothing like that currently defined in ARMv8.
The Cortex-A8 and some older ARM processors have the facility to lock down parts of the L2 cache. It isn't in newer processors, but Cortex-M processors can use TCM (Tightly-Coupled Memory) to ensure some routines or interrupts are handled efficiently without waiting for DRAM or caches. That is quite a different target though from what Intel aims for with reserving parts of the L3 cache in servers.
I can see ARM would probably need to think a bit about exactly how such a facility would be used and how best to control it, and it would probably be mainly a standardization process for them worrying about things like multiprocessors and virtualization and different models and switching overheads rather than anything directly related to designing a processor. So it may need a partner to say they want the facility and would work to implement it to get them to do something about this.
Well it seems that Qualcomm's server chips implements this, see the article in AnandTech
Analyzing Falkor’s Microarchitecture: A Deep Dive into Qualcomm’s Centriq 2400 for Windows Server and Linux
second page on L3 quality of service extensions.