Hello,
Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ?I have some 2 implementation of this routines, one is called L1 and the other L2C-310.
I am just not sure if using L1 will be good enough, or is it that cortex a8 internal L2 still need to be flushed/invalidate even when using cortex a8.
Thank you!
Ran
Hi Ran,
I suspect the routines are taken from an A9 codebase where the L2 cache is an external device (the L2C-310) so you need a special routine - you definitely don't need this for A8.
I also suspect that the "L1" routine is really an internal cache flush routine, in which case it will probably work for the A8's L1 and L2. If the routine flushes an address range it will use an instruction like DCCMVAU or DCCMVAC which should "just work (TM)" as they don't rely on knowing the cache topology.
If the routine is a full cache flush it will use set/way operations (DCCSW) which do need to know how many levels of cache there are. Well written code should self-discover this by reading some ID registers and just work but if the routine hardcodes a single level it won't.
TLDR; You don;t need the L2C-310 routine, the "L1" routine might work.
Pete.