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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3627 Questions
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  • Not Answered

    Cortex-A53 L2 cache invalidation 0

    • Cortex-A53
    • Cache Management
    • Cache Architecture
    3143 views
    2 replies
    Latest over 4 years ago
    by Kalex
  • Not Answered

    M7 atomic operation faults on non cacheable memory 0

    • 5 (BusFault)
    • STM32 F7
    8136 views
    8 replies
    Latest over 4 years ago
    by Clay McClure
  • Not Answered

    Having trouble with interrupt latency and cycle time in M0+ 0

    • Interrupt Handling
    • Clocking Structures & Timing Mechanisms
    • Cortex-M0+
    1170 views
    0 replies
    Started over 4 years ago
    by KhanZ
  • Not Answered

    GICv2 Interrupt auto deassertion - Cortex-R5 0

    • GICv2
    • Cortex-R5
    1260 views
    0 replies
    Started over 4 years ago
    by ijahmad
  • Not Answered

    How does Realm VM deal with interrupts? 0

    1353 views
    0 replies
    Started over 4 years ago
    by echov8
  • Suggested Answer

    Cortex A53 and AMP Asynchronous Multiprocessing 0

    • Cache coherency
    • Cache Coherent Interconnect
    • Cortex-A
    5566 views
    5 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    Non-secure call Secure used SG instruction cause Hard Fault 0

    3785 views
    6 replies
    Latest over 4 years ago
    by Thomas Coding
  • Suggested Answer

    Conditional Non-branch Instructions 0

    • ETM
    2238 views
    2 replies
    Latest over 4 years ago
    by Willy Wolff Arm Employee Badge
  • Not Answered

    How high is the precision of fixed-point processors for floating-point numbers? 0

    • Processors
    1523 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Failed to Generate Application Project in Vitis 2020.1 for Cortex M1 softcore processor on Arty A7 100T FPGA. 0

    • FPGA Xilinx
    • Cortex-M1
    • FPGA
    3621 views
    0 replies
    Started over 4 years ago
    by Vybhav MN
  • Answered

    How to read/write an I/O port in aarch64? 0

    • AArch64
    • Arm64
    7791 views
    3 replies
    Latest over 4 years ago
    by LucasBarros90
  • Not Answered

    Multiple ARM CPU in the same Motherboard 0

    3933 views
    2 replies
    Latest over 4 years ago
    by sidereal
  • Answered

    How to compute a cache size? +1

    9289 views
    2 replies
    Latest over 4 years ago
    by ted
  • Suggested Answer

    What's the meaning of the entry of exception vector for ARM-VA7 0

    • Armv7-A
    3110 views
    4 replies
    Latest over 4 years ago
    by asic_xuan
  • Not Answered

    the halt of Systick 0

    • CoreSight Architecture
    • 15 (SysTick)
    1874 views
    2 replies
    Latest over 4 years ago
    by asic_xuan
  • Not Answered

    Cortex M33 Return to Non Secure Thread from Secure SVC 0

    • TrustZone for Armv8-M
    • Cortex-M33
    2366 views
    0 replies
    Started over 4 years ago
    by mcak
  • Not Answered

    How do we correctly use the CMSIS-DSP functions that have fixed-point (Qx) input/outputs? 0

    • Digital Signal Processor (DSP)
    • CMSIS
    3568 views
    1 reply
    Latest over 4 years ago
    by Annie
  • Answered

    Initialization an array of 24-bit signed integers 0

    • Cortex-M3
    • Arm Assembly Language (ASM)
    3528 views
    5 replies
    Latest over 4 years ago
    by WestfW
  • Not Answered

    Setting Non-Secure Memory from Secure Memory on TrustZone for Armv8-m 0

    • TrustZone for Armv8-M
    • Cortex-M33
    4335 views
    4 replies
    Latest over 4 years ago
    by mcak
  • Answered

    Wrong interrupt vector called 0

    • Interrupt Handling
    • Interrupt Controllers
    • Cortex-M4
    4882 views
    10 replies
    Latest over 4 years ago
    by Stric
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