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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3631 Questions
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  • Answered

    MPU vs TrustZone-M 0

    • TrustZone
    • Armv8-M
    • Memory
    19200 views
    4 replies
    Latest over 8 years ago
    by BlueP
  • Answered

    ARM7TDMI memory spaces +1

    • Cortex-M
    4229 views
    1 reply
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Cortex-A8 Pipelined cache maintenance 0

    • Cache
    • Cortex-A
    • Cortex-A8
    4556 views
    2 replies
    Latest over 8 years ago
    by Paddu
  • Answered

    Detect RESET cause on Cortex M3 (STM32F107)? +1

    • Cortex-M3
    • Cortex-M
    12620 views
    8 replies
    Latest over 8 years ago
    by Terje
  • Answered

    What does "CMSDK_GPIO1->ALTFUNCSET = (1<<5);" do? 0

    • CMSDK
    • Cortex-M
    5028 views
    3 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Hard Fault on Cortex M0 +1

    • Cortex-M0
    • Cortex-M
    5392 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    CM4: Write buffer with enabled MPU +1

    • Cortex-M
    • Cortex-M4
    9607 views
    4 replies
    Latest over 8 years ago
    by Matic
  • Answered

    Where could I find a good start for studying Memory Types and Attributes as well as Monitors and semaphores ? +1

    • AMBA
    • Cortex-M3
    • Cortex-M
    3142 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Cortex M4 Conditional Branch - Pipeline +1

    • Cortex-M
    • C
    • Cortex-M4
    8533 views
    5 replies
    Latest over 8 years ago
    by fede_cip
  • Answered

    SOC for DVBC +1

    4713 views
    2 replies
    Latest over 8 years ago
    by Mellingen_CH
  • Answered

    Software interrupt generation on Cortex M33. +1

    • Cortex-M
    • Cortex-M33
    7324 views
    3 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Suggested Answer

    Is Cache Stashing introduced in DynamIQ similar to IO coherency? 0

    • Cache coherency
    • DynamIQ Shared Unit (DSU)
    7548 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Is it possible the direct device's interrupt assignment to the guest OS instead of being routed by the hypervisor to the guest OS? 0

    • Armv8-A
    • Generic Interrupt Controller
    5948 views
    2 replies
    Latest over 8 years ago
    by Jorge
  • Answered

    CM4: Can processor halt itself by writing DHCSR +1

    • Cortex-M
    • Cortex-M4
    • AHB
    5554 views
    2 replies
    Latest over 8 years ago
    by Vanhealsing
  • Answered

    About watch point debug excption on Cortex-A53 +3

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    12810 views
    6 replies
    Latest over 8 years ago
    by tao.zeng
  • Answered

    [CM4] Best general way to handle a hardfault/lockup 0

    • Armv7 Exception Model
    • Cortex-M
    • Cortex-M4
    8575 views
    3 replies
    Latest over 8 years ago
    by sfoster
  • Suggested Answer

    What is the relationship between UART and printf within retarget? 0

    • Cortex-M3
    • Cortex-M
    8268 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Suggested Answer

    Where to find the execution cycles of Cortex m7 instruction 0

    • Cortex-M0
    • Cortex-M7
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    26621 views
    9 replies
    Latest over 8 years ago
    by tyskin
  • Not Answered

    Intercore interrupts on a53 between EL1 and EL3 0

    • Cortex-A53
    • Cortex-A
    6079 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Cache Allocation Technology 0

    • AArch64
    • Cache
    • Cortex-A
    • Cortex-A8
    • AArch32
    7241 views
    2 replies
    Latest over 8 years ago
    by daith
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