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CM4: Write buffer with enabled MPU

Matic

Hello,

I have a question regarding Memory protection unit on Cortex M4 (STM32F3 MCU). This is pretty simple single core MCU without caches. I implemented MPU based on instructions in Definitive guide to the ARM Cortex-M4. It is stated there that the bufferable attribute of the memory, if it is defined by the MPU and the MPU is enabled, has higher priority than the default condition.

So, I defined a peripheral region (addresses from 0x40000000 - 0x5FFFFFFF) as a separate MPU region (full access, execute never) with bufferable attribute set. Is there any chance to see or to distinguish the behaviour if I set bufferable attribute or not?

The same for internal SRAM. First of all, is SRAM bufferable at all? And how to see difference if I set this attribute for SRAM or not?

There is also a prefetch block which is used for instruction fetches over the ICode bus. Is this somehow connected with cacheable attribute. Do I have to define a cacheable attribute for Flash, if it is coverd by the MPU?

Thank you in advance,

Matic

Parents
  • 0 in reply to Joseph Yiu

    Thank you. Your response is very valuable to me.

    I did a bit of testing (measured CPU clocks via debugger for 500 program cycles):

    1. Write Buffer disabled (DISDEFWBUF set)  and MPU not used: 1.696.833

    2. Write Buffer enabled and MPU not used: 1.676.663

    3. Write Buffer enabled and MPU enabled with settings below:   1.695.451

    #define FLASH_MEMORY_ATT              (MPU_RASR_C_Msk)  

    #define PERIPHERALS_ATT                   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)

    #define INT_SRAM_MEMORY_ATT        0

    4. Write Buffer enabled and MPU enabled with settings below:   1.676.825

    #define FLASH_MEMORY_ATT              (MPU_RASR_C_Msk)  

    #define PERIPHERALS_ATT                   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)

    #define INT_SRAM_MEMORY_ATT        (MPU_RASR_C_Msk | MPU_RASR_S_Msk)

    5. Write Buffer enabled and MPU enabled with settings below:   1.676.832

    #define FLASH_MEMORY_ATT              (MPU_RASR_C_Msk)  

    #define PERIPHERALS_ATT                   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)

    #define INT_SRAM_MEMORY_ATT        (MPU_RASR_B_Msk  |  MPU_RASR_C_Msk | MPU_RASR_S_Msk)

    So, there is no obvious differnece, if B attribute is 1 for SRAM, but there is some difference if none of C or B is set.

    Regards

Reply
  • 0 in reply to Joseph Yiu

    Thank you. Your response is very valuable to me.

    I did a bit of testing (measured CPU clocks via debugger for 500 program cycles):

    1. Write Buffer disabled (DISDEFWBUF set)  and MPU not used: 1.696.833

    2. Write Buffer enabled and MPU not used: 1.676.663

    3. Write Buffer enabled and MPU enabled with settings below:   1.695.451

    #define FLASH_MEMORY_ATT              (MPU_RASR_C_Msk)  

    #define PERIPHERALS_ATT                   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)

    #define INT_SRAM_MEMORY_ATT        0

    4. Write Buffer enabled and MPU enabled with settings below:   1.676.825

    #define FLASH_MEMORY_ATT              (MPU_RASR_C_Msk)  

    #define PERIPHERALS_ATT                   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)

    #define INT_SRAM_MEMORY_ATT        (MPU_RASR_C_Msk | MPU_RASR_S_Msk)

    5. Write Buffer enabled and MPU enabled with settings below:   1.676.832

    #define FLASH_MEMORY_ATT              (MPU_RASR_C_Msk)  

    #define PERIPHERALS_ATT                   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)

    #define INT_SRAM_MEMORY_ATT        (MPU_RASR_B_Msk  |  MPU_RASR_C_Msk | MPU_RASR_S_Msk)

    So, there is no obvious differnece, if B attribute is 1 for SRAM, but there is some difference if none of C or B is set.

    Regards

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