• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 3 replies
  • Subscribers 351 subscribers
  • Views 6828 views
  • Users 0 members are here
Options
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Software interrupt generation on Cortex M33.

sdiwakar

Hi,

On Cortex M33 , i am trying to check software interrupt functionality. Below is the CMSIS APIs i used.  Note that the CPU is in secure world and secure VTOR is being configured.

Also, ITNS config for this line is set to secure.

NVIC_SetPriorityGrouping(0);
 NVIC_SetPriority(6, 1);
 NVIC_EnableIRQ(6);
 NVIC_SetVector(6, (uint32_t)SwIRQ_Handler);
  NVIC->STIR = 6;

On ARM FastModel, when i ran this test, i could see that the IRQ gets generated as expected but, i don't see the same on HW.

In HW, IRQ line 6 is tied to 0.

assign cpu_irq_i[6] = 1'b0 ;

Before, i start suspecting the RTL, i wanted to understand , are there any unwritten rules on what interrupt lines can be used for Software interrupt purpose ?

I did find a related link on the community but i couldn't get the answer i was looking for. Hence, reposting the question.

Thanks,

Diwakar

0