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Cortex M4 Conditional Branch - Pipeline

fede_cip

Hello all!

So I'm working on a development with a Cortex M4 and there is something i don't understand, I was hoping someone could help clarify this:

This is the code I' using

(Assume R3 content is 1, R6 R8 the address needed to set PIN1, and R11 R9 the address needed to set PIN2)

asm ( "CMP R3,#0 \n\t");

asm ( "BNE NCycles_CapDelay2 \n\t");

/*asm ( "NOP \n\t"

            "NOP \n\t" 

            "NOP \n\t");*/<-----------------------------------

asm ( "STR R6,[R8] \n\t"); //PIN1 SET

asm ( "STR R11, [R9] \n\t" //PIN2 SET

asm ( "B SOMEWHERE_ELSE\n\t");

asm ("NCycles_CapDelay2: \n\t");

/*asm ( "NOP \n\t"

            "NOP \n\t"

            "NOP \n\t");*/<-----------------------------------

"STR R6,[R8] \n\t"); //PIN1 SET


asm ("LOOP_NCycles_CapDelay2: \n\t");

asm ( "SUBS R3, #1 \n\t");

asm ( "bne LOOP_NCycles_CapDelay2 \n\t");

asm ( "STR R11, [R9] \n\t" //PIN2 SET

The thing is: If i leave the NOPs commented, the time between PIN1 set and PIN2 set is 7 cycles, and if i UNcomment those NOPs, the time is 1 Cycle (measured externally with OSC)

And when R3=0, the time difference is 0 Cycles (UNcommented NOPs) to 1 Cycle (commented NOPs)

Any ideas with what is happening with the pipeline and conditional Branches here?

Thanks for any ideas.

BR

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