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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    Booting bare metal application on cortex A57 with u-boot +2

    • Cortex-A57
    • U-Boot
    • Armv8
    • Baremetal
    14455 views
    4 replies
    Latest over 8 years ago
    by vdupre
  • Answered

    Aarch64 llvm unrecognized instruction mnemonic +1

    • Android
    • LLVM
    • Arm64
    19881 views
    6 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Trapping IRQ from Secure World Firmware to Normal World Rich OS over Monitor Vector Table 0

    • Address
    • CHI
    • TrustZone
    • Armv8-M
    • Interrupt
    13822 views
    4 replies
    Latest over 8 years ago
    by daith
  • Answered

    How to view instruction word - instruction currently being executed. +1

    3470 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    I need Info regarding DVFS and DPM in ARM Cortex-A15 +1

    • Processing Techniques
    • Intelligent Energy Controller
    • Cortex-A15 FVP
    • Power Management Kits
    • Processor Architecture
    • Processors
    5439 views
    1 reply
    Latest over 8 years ago
    by Zhifei Yang
  • Answered

    generic timer difference armv8a and cortex-a53 0

    7419 views
    3 replies
    Latest over 8 years ago
    by heg104434
  • Answered

    Cortex a15 disable non-blocking cache +1

    4607 views
    2 replies
    Latest over 8 years ago
    by pa007
  • Answered

    Square root calculation results. FPU logic of A15 and A7 CPUs on Odroid-XU3 board. +1

    • Cortex-A15
    • Cortex-A7
    5805 views
    2 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Starting with Arm assembly to obtain machine code +1

    • Armv8
    • Arm Assembly Language (ASM)
    6464 views
    1 reply
    Latest over 8 years ago
    by Myy
  • Answered

    RIT Interrupt in Keil uVision +1

    3781 views
    1 reply
    Latest over 8 years ago
    by dameash
  • Answered

    ARMV8 48-vs-52-bit mode +1

    4093 views
    1 reply
    Latest over 8 years ago
    by daith
  • Answered

    Why is there no vector integer divide in SIMD instructions ? +1

    • SIMD and Vector Processing Instructions
    11479 views
    3 replies
    Latest over 8 years ago
    by daith
  • Answered

    Cortex M0+ on teensy LC, USB not working. +1

    2959 views
    1 reply
    Latest over 8 years ago
    by yikestone
  • Answered

    What works as a data memory barrier? +1

    6880 views
    4 replies
    Latest over 8 years ago
    by kevinlayer
  • Answered

    Why is string defined with half '0's? +1

    • Cortex-M4
    3854 views
    1 reply
    Latest over 8 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    Cortex A53 Out of Order? +1

    • Cortex-A53
    • Cortex-A
    8016 views
    3 replies
    Latest over 8 years ago
    by pizza
  • Answered

    ARM Processor board and Programming +1

    4242 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Cortex M0+ what means "optionally shifted" at some instructions like EOR (register) +1

    3803 views
    2 replies
    Latest over 8 years ago
    by Volker Kugler
  • Answered

    Speculative Branching. +1

    • Cortex-M3
    8072 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Security State transitions - Processor Mode +2

    • ANSI
    • CHI
    • Security
    • TrustZone
    • Armv8-M
    34961 views
    11 replies
    Latest over 8 years ago
    by raghu.ncstate
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
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  • AXI
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  • Cortex-A
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  • Linux
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  • NEON
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