Hi,
When core makes a transaction, NS signal is sent on AXI bus depending on the SCR.NS bit.
But when DMA transaction is issued, how the NS bit is propagated on the AXI bus ?
Thanks
Sahil
The question is too general. It depends on the respective implementation of the DMA. Check your SoC manual to see if the DMA can be used in secure or normal word and if it does support NS bit.
since you mention AXI, I presume you are talking about Cortex-A.
This group is focused on Cortex-M, so I will reply in relation to that.
(Please post all Cortex-A questions to the processors group. thanks)
AMBA 5 AHB5 is the new interface standard used by Cortex-M23 and Cortex-M33 to propagate the security across the system.
A DMA block that supports AHB5 will generate and interpret the bus signals correctly as fares security is concerned.
The standard specification is public and so are the technical reference manuals for both Cortex-M23 and Cortex-M33 so that you can easily see the full technical details .