Hello people,
we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one handles DMA configurations and its interrupts. We have noticed that only when we completely disable L2 cache DMA transfers are working as expected. However, disabling L2 cache also affects some parts of lwIP, so we were wondering whether is possible to somehow disable L2 cache only for CPU1? We tried to put entire DDR segment which is seen by CPU1 as non cacheable with function Xil_SetTlbAttributes and value 0x14de2 (S=b1, TEX=b100 AP=b11, Domain=b1111, C=b0, B=b0), however this doesn't help.
Best regards,Nenad
Should I mark entire DDR as non cachable or only the segment that is seen by core1? MMU is enabled for core1. Thanks for the reply, I have put this task on hold, since it's not completely a blocker for a project, so I haven't moved a lot from this point.
I recommend to mark all parts of the memory which should not be accessed by core1 as invalid in the core1-MMU table. And all other parts it uses as non-cacheable.
Maybe you can set it INNER cachable and outer non-cachable, but never tried it.
What do you exactly think by "invalid" memory? These are the attributes I can set in MMU table: