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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3588 Questions
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  • Answered

    CPU Reset during a Debug session +1

    • Armv6-M
    • Cortex-M
    22356 views
    27 replies
    Latest over 10 years ago
    by Sayed Abdulhayan
  • Answered

    ARM Cortex A9 boot from spi-flash 32M +1

    • Cortex-A9
    • Cortex-A
    • Linux
    5753 views
    2 replies
    Latest over 10 years ago
    by Daniel
  • Answered

    Which is best ARM starter board for 32 Bit 3D printer? +1

    • 32-bit
    • Cortex-M
    • Cortex-M4
    4219 views
    1 reply
    Latest over 10 years ago
    by Clovis Fritzen
  • Answered

    Return address from FIQ_Handler. Do we come back to the next instruction? 0

    • Armv7-A
    • Armv7-R
    • Cortex-M
    4158 views
    3 replies
    Latest over 10 years ago
    by Harshdeep
  • Answered

    Cortex-A8 boot up cpsr status 0

    • Cortex-A
    • Cortex-A8
    • Linux
    5207 views
    3 replies
    Latest over 10 years ago
    by Harshdeep
  • Answered

    How to use the performance monitor of Cortex-A9? 0

    • Cortex-A9
    • Cortex-A
    6299 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Problems with  AXI4  write data channel 0

    • AMBA
    • AXI4
    6681 views
    6 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Not Answered

    Cortex-M7 "zero overhead loop" 0

    • Cortex-M7
    • Cortex-M
    • Cortex-M4
    10403 views
    6 replies
    Latest over 10 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    brk instrustion +1

    • Cortex-A53
    • AArch64
    • Cortex-A
    • C
    5746 views
    1 reply
    Latest over 10 years ago
    by daith
  • Answered

    ARM v8 secondary CPU bootup 0

    • AArch64
    • Armv8-A
    • TrustZone
    • C
    8901 views
    4 replies
    Latest over 10 years ago
    by Harish G
  • Answered

    shareability memory attribute 0

    • Cortex-A57
    • Cortex-A
    • Cortex-A8
    7128 views
    2 replies
    Latest over 10 years ago
    by hostia
  • Answered

    How to acknowledge/clear active interrupt in Cortex-M4 +1

    • Cortex-M
    • Cortex-M4
    15759 views
    4 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    ARMv8 EL1 MMU 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    10748 views
    6 replies
    Latest over 10 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    NEON SIMD Dn Register and Parallel Operations 0

    • 32-bit
    • NEON
    5779 views
    3 replies
    Latest over 10 years ago
    by Kenrick Aylesworth
  • Answered

    Does load/store-exclusive violate Hypervisor Transparency? 0

    • Armv7-A
    • Armv8-A
    4780 views
    1 reply
    Latest over 10 years ago
    by Matt Sealey Arm Employee Badge
  • Not Answered

    NEON-Advanced SIMD vs. SIMD 0

    • Armv6-A
    • NEON
    • Cortex-A
    15660 views
    5 replies
    Latest over 10 years ago
    by daith
  • Answered

    NEON SIMD Register Diagram 0

    • NEON
    • Cortex-A
    5690 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    The reason why the exception frame forms on PSP? 0

    • Cortex-A
    • Cortex-M
    11947 views
    15 replies
    Latest over 10 years ago
    by daith
  • Answered

    How to enable Neon in cortex A8? +1

    • NEON
    • Cortex-A
    • Cortex-A8
    13864 views
    9 replies
    Latest over 10 years ago
    by daith
  • Answered

    What is the effect of LDR r0, [r5, r6, LSL r2] 0

    • 32-bit
    8926 views
    2 replies
    Latest over 10 years ago
    by Phil Greco
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