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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3586 Questions
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  • Answered

    Transition to secure monitor flow on ARMv8 +1

    • ARMv8 Exception Model
    • Security
    • Armv8
    • Armv8-A
    6023 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Is there any tools which can convert memory to assemble code? +1

    • AArch64
    • T32 (Thumb)
    4709 views
    2 replies
    Latest over 8 years ago
    by tao.zeng
  • Answered

    IAR Compilation error +1

    • Cortex-M
    • Cortex-M4
    2737 views
    1 reply
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Cortex M4 L1 data cache policy +1

    • Cortex-M
    • Cortex-M4
    8265 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    SMC flow on ARMv8 0

    • ARMv8 Exception Model
    • Armv8-A
    6914 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    AXI write outstanding transactions causing problem in image data 0

    • AMBA 3
    5894 views
    1 reply
    Latest over 8 years ago
    by petehaw Arm Employee Badge
  • Answered

    Transition to secure monitor flow on ARMv8 0

    • ARMv8 Exception Model
    • Armv8
    • Armv8-A
    • Cortex-A
    • Cotex-A72
    • Baremetal
    7151 views
    4 replies
    Latest over 8 years ago
    by Umair Khan
  • Suggested Answer

    Stable set of ARM MCU, libraries, and Dev Environment 0

    • Keil
    • IDEs and Tool Suites
    • Cortex-M
    • Software Development
    6715 views
    5 replies
    Latest over 8 years ago
    by Sebastian Floss
  • Not Answered

    Using st1 to copy 3 floats from NEON register 0

    3854 views
    2 replies
    Latest over 8 years ago
    by lefty
  • Not Answered

    Purpose of SAU in Multi-Master System 0

    • ACE
    • Security
    • TrustZone
    • System Design
    • Community
    • Armv8-M
    • Secure Transactions
    • Memory
    8966 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    ARM Cortex-A53 System Register +1

    • Cortex-A53
    5822 views
    4 replies
    Latest over 8 years ago
    by M1509
  • Answered

    When to enable ARM Cortex A8 L1 cache parity detection 0

    4285 views
    3 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Cortex A9 (IMX6) : Enabling branch prediction aborts +1

    13305 views
    10 replies
    Latest over 8 years ago
    by Gopu
  • Answered

    Multiple voltage levels for a Single Frequency in ARM A15 processors +1

    4259 views
    2 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Not Answered

    configuration clock using CMSIS stm32f7 ? 0

    3368 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    hello , How to enable / disable a global interrupt on cortex M7 +1

    • Interrupt
    29614 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Ignored bits in ARMv7a LPAE / ARMv8 Table descriptors 0

    5354 views
    4 replies
    Latest over 8 years ago
    by Vincent Siles
  • Suggested Answer

    Hardfault issue 0

    5138 views
    4 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    ARMv7 Vs ARMv8 AArch32 Performance improvement +2

    • Armv7
    • Armv8
    • AArch32
    16748 views
    5 replies
    Latest over 8 years ago
    by damalinxp
  • Answered

    Questions regarding NEON 0

    • DSP
    • NEON
    6679 views
    3 replies
    Latest over 8 years ago
    by gravi
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
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  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
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  • Cortex-M0
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  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone