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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    APB : About the validation of APB Performance monitor? 0

    1068 views
    1 reply
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Cortex-R52+ floating-point register pop and push 0

    • fpu
    • Floating-Point Execution
    • Cortex-R52+
    1628 views
    3 replies
    Latest 10 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    APB : Different version of Master and Slave in APB? 0

    1250 views
    1 reply
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    APB : How does Single Master and Multiple Slaves Work in APB? 0

    2222 views
    1 reply
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    How to Read Secure fields of the CONTROL Register from GDB? 0

    • TrustZone-M
    • TrustZone for Armv8-M
    • Trusted Execution Environment (TEE)
    • Cortex-M
    • Cortex-M33
    561 views
    0 replies
    Started 10 months ago
    by kiko
  • Suggested Answer

    Cortex-M4 memory ordering 0

    • Memory ordering
    • Cortex-M4
    1382 views
    1 reply
    Latest 10 months ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Origin of non-standard AMBA signals AHB-Lite 0

    • AMBA 3
    • Cortex-M4
    1143 views
    1 reply
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Why my "double" type data is always positive? 0

    • data
    • a53
    • Cortex-A
    • Cortex-M
    • m40
    1312 views
    2 replies
    Latest 10 months ago
    by Kael Hong
  • Not Answered

    Write issuing capability about dsu for a single arm a55 0

    521 views
    0 replies
    Started 10 months ago
    by jingbin zhang
  • Not Answered

    Need help to choose MCU 0

    583 views
    0 replies
    Started 10 months ago
    by Sharath HS
  • Not Answered

    Linker errors compiling for Cortex-M33 0

    • compiler
    • Cortex-M3
    • GNU Arm
    • Cortex-M33
    • Linking Error
    869 views
    0 replies
    Started 10 months ago
    by Jorg Wieme
  • Not Answered

    ARM SBSA sbsa_gwdt watchdog timer driver Pretimeout feature 0

    1078 views
    1 reply
    Latest 10 months ago
    by Akshay Dharmapuri
  • Answered

    [APB5]What is this limitation about three logic levels available in timing allowances for generating parity bit? 0

    1057 views
    1 reply
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 Unaligned transfer WRITEs and READs 0

    • AMBA
    • AXI4
    • unaligned
    2590 views
    3 replies
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 unaligned transfer +1

    3260 views
    4 replies
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    M55 PMU cycle counter returning 0. 0

    • Cortex-M55
    • Armv8.1-M
    • pmu
    • cycle count
    • Cortex-M
    • Armv8-M
    742 views
    0 replies
    Started 10 months ago
    by Karthik Kumar G R
  • Not Answered

    ETE Instruction Trace Configuration 0

    • Debug and Trace
    579 views
    0 replies
    Started 10 months ago
    by Lauren Ho
  • Not Answered

    Is the SYST_CVR (0xE000E018) register accessible in USER mode ? 0

    1046 views
    2 replies
    Latest 10 months ago
    by Hicham Boutlalek
  • Suggested Answer

    TxnID in AMBA CHI Chip-to-Chip 0

    • CHI
    1639 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Configuration Control Register (CCR). 0

    660 views
    0 replies
    Started 11 months ago
    by Pragathi Simha
<>
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