Hello everyone,
We have been developing a bare-metal hypervisor for Cortex A53.
In this hypervisor, we use the instruction "AT S12E1R , Xn" to translate Virtual Addresses (provided by the Guest OS at EL1) to Physical addresses.
At EL1, we only configure the stage 2 MMU translation, and it has been working fine when booting with u-boot.
However , we recently changed our implementation to use our custom boot and this started to raise problems:
- The CPU core shuts down when running the "AT S12E1R, x0" with x0 having any virtual address (or IPA since we are only using stage 2).
So far we have tried to enable EL3 MMU or stage 1 EL1 MMU, but nothing worked.
We have cross checked the architecture configuration registers using u-boot and our boot and we did not find any misplaced configuration that would justify this behavior.
Is there anything we might be overlooking?
Thanks in advance.
Could there be some missing configuration?
Hi Martin,
Thanks for replying.
By shutdown I actually mean the core stops responding and we need to reset it in order to get it running again.
The addresses we are using are mapped to the DDR, like 0x91000000, and accessing them is OK at EL2 with MMU enabled.
I think we are having what you describe as "hanging core" and seems like a request to the memory system is not completing when using S1 and S2 MMU at EL1.
To confirm, we have attempted, with Lauterbach debugger, to set the core to EL1 after configuring stage 2 MMU at EL1.
As soon as we read from memory, the debugger displays a "debug port" error and disconnects, and we are unable to reconnect to the core.
We've have checked all the registers associated with S2 and S1 MMU at EL1 and EL2 (listed below), and no register seemed to have a configuration that could compromise the MMU behavior.
Could we be missing a check on any other register?
Thanks for the support.