Where does the write data store during an outstanding transaction before master send write address? If the data stored in memory, what is the memory size?
If write data is sent before the write address (perfectly legal), where that data might be stored depends on where in the system you are looking.
For example if the AXI manager sends the data before the address, the interconnect logic won't know where to route that data through to until it has seen an address. So the interconnect could have buffering or registering in the input stage that could hold some write data until an address has been received. Or if the interconnect doesn't have any write data storage in the input stage it would just drive WREADY low to stall any write data transfers until AWVALID is seen high to say where to route the data.
Or if the transaction address has been received by the interconnect and the transfer routed through to the relevant destination port, BUT then there are additional delays (registering) on the AW channel after all the address decoding, you could still see W transfers before AW at the final destination, so then you could have a write buffer (registering) built into the target to temporarily hold that data, or to keep things simple, stall the W transfers by the AXI subordinate target holding WREADY low until it knows what to do with the data.
So we are not looking at storing this write data in standard "memory", but instead either building in buffering or registering on the W channel, or just stalling the W transfers using WREADY low until the AW transfer has been received.