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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Answered

    APB : Different version of Master and Slave in APB? 0

    1505 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    APB : How does Single Master and Multiple Slaves Work in APB? 0

    3125 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    How to Read Secure fields of the CONTROL Register from GDB? 0

    • TrustZone-M
    • TrustZone for Armv8-M
    • Trusted Execution Environment (TEE)
    • Cortex-M
    • Cortex-M33
    713 views
    0 replies
    Started over 1 year ago
    by kiko
  • Suggested Answer

    Cortex-M4 memory ordering 0

    • Memory ordering
    • Cortex-M4
    1878 views
    1 reply
    Latest over 1 year ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Origin of non-standard AMBA signals AHB-Lite 0

    • AMBA 3
    • Cortex-M4
    1382 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Why my "double" type data is always positive? 0

    • data
    • a53
    • Cortex-A
    • Cortex-M
    • m40
    1522 views
    2 replies
    Latest over 1 year ago
    by Kael Hong
  • Not Answered

    Write issuing capability about dsu for a single arm a55 0

    601 views
    0 replies
    Started over 1 year ago
    by jingbin zhang
  • Not Answered

    Need help to choose MCU 0

    655 views
    0 replies
    Started over 1 year ago
    by Sharath HS
  • Not Answered

    Linker errors compiling for Cortex-M33 0

    • compiler
    • Cortex-M3
    • GNU Arm
    • Cortex-M33
    • Linking Error
    1209 views
    0 replies
    Started over 1 year ago
    by Jorg Wieme
  • Not Answered

    ARM SBSA sbsa_gwdt watchdog timer driver Pretimeout feature 0

    1441 views
    1 reply
    Latest over 1 year ago
    by Akshay Dharmapuri
  • Answered

    [APB5]What is this limitation about three logic levels available in timing allowances for generating parity bit? 0

    1228 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 Unaligned transfer WRITEs and READs 0

    • AMBA
    • AXI4
    • unaligned
    3704 views
    3 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 unaligned transfer +1

    3932 views
    4 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    M55 PMU cycle counter returning 0. 0

    • Cortex-M55
    • Armv8.1-M
    • pmu
    • cycle count
    • Cortex-M
    • Armv8-M
    868 views
    0 replies
    Started over 1 year ago
    by Karthik Kumar G R
  • Not Answered

    ETE Instruction Trace Configuration 0

    • Debug and Trace
    679 views
    0 replies
    Started over 1 year ago
    by Lauren Ho
  • Not Answered

    Is the SYST_CVR (0xE000E018) register accessible in USER mode ? 0

    1211 views
    2 replies
    Latest over 1 year ago
    by Hicham Boutlalek
  • Suggested Answer

    TxnID in AMBA CHI Chip-to-Chip 0

    • CHI
    1871 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Configuration Control Register (CCR). 0

    836 views
    0 replies
    Started over 1 year ago
    by Pragathi Simha
  • Not Answered

    Can Cortex-M33 MCUs enable SAU and MPU_NS simultaneously? 0

    • mpu
    • Cortex-M
    • Cortex-M33
    • Armv8-M
    • SAU
    693 views
    0 replies
    Started over 1 year ago
    by kiko
  • Answered

    Exception return issues with Cortex-M3 on STM32F103C8T6 0

    • Exception Handling
    • Interrupt Handling
    • stm32f103
    • Cortex-M3
    • STM32
    • Interrupt
    3183 views
    2 replies
    Latest over 1 year ago
    by Nancen Li
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