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What's the relationship between exclusive access and memory cacheable in Cortex A53?

Emmy0

Hello community and experts,

         I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.

         When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal type+non-cacheable, it will generate exception when execute 'ldaxr'.

        Must the memory of exclusive instructions access be cacheable in Cortex-A53?

        Thanks for your attention!

Best Regards,

Emmy

  

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  • 0

    Thanks for 42Bastian Schick's and Peter Rielly's explainations.

    It seems my A53 system does not support exclusiveness in non-cached memory.

    Is there any method to verify cache's correctness and stability?

    Thanks for your attention!

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  • 0

    Thanks for 42Bastian Schick's and Peter Rielly's explainations.

    It seems my A53 system does not support exclusiveness in non-cached memory.

    Is there any method to verify cache's correctness and stability?

    Thanks for your attention!

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