• State Suggested Answer
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 350 subscribers
  • Views 6694 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

What's the relationship between exclusive access and memory cacheable in Cortex A53?

Emmy0

Hello community and experts,

         I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.

         When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal type+non-cacheable, it will generate exception when execute 'ldaxr'.

        Must the memory of exclusive instructions access be cacheable in Cortex-A53?

        Thanks for your attention!

Best Regards,

Emmy

  

Parents
  • 0

    Thanks for 42Bastian Schick's and Peter Rielly's explainations.

    It seems my A53 system does not support exclusiveness in non-cached memory.

    Is there any method to verify cache's correctness and stability?

    Thanks for your attention!

Reply
  • 0

    Thanks for 42Bastian Schick's and Peter Rielly's explainations.

    It seems my A53 system does not support exclusiveness in non-cached memory.

    Is there any method to verify cache's correctness and stability?

    Thanks for your attention!

Children
No data