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Hello community and experts,
I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.
When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal type+non-cacheable, it will generate exception when execute 'ldaxr'.
Must the memory of exclusive instructions access be cacheable in Cortex-A53?
Thanks for your attention!
Best Regards,
Emmy
For cacheable, shareable memory the A53 (and all the other MPCores) will manage the exclusive access internally.
For non-cacheable memory the transaction is sent out onto the bus with extra metadata identifying it as an exclusive transaction. It then relies on an external Global Monitor implemented somewhere in the memory system dealing with the exclusiveness.
Some DDR controllers implement a monitor, some don't, so if non-cacheable exclusives 'work' or not is a system level thing.