Hello community and experts,
I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.
When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal type+non-cacheable, it will generate exception when execute 'ldaxr'.
Must the memory of exclusive instructions access be cacheable in Cortex-A53?
Thanks for your attention!
Best Regards,
Emmy
The ARMv8-A manual states this:
"For shareable memory locations, in some implementations and for some memory types, the properties of the global monitor require functionality outside the PE. Some system implementations might not implement this functionality for all locations of memory. In particular, this can apply to:• Any type of memory in the system implementation that does not support hardware cache coherency.• Non-cacheable memory, or memory treated as Non-cacheable, in an implementation that does support hardware cache coherency."
Seems, as it could be that A53 does not support exclusiveness in non-cached RAM.
For cacheable, shareable memory the A53 (and all the other MPCores) will manage the exclusive access internally.
For non-cacheable memory the transaction is sent out onto the bus with extra metadata identifying it as an exclusive transaction. It then relies on an external Global Monitor implemented somewhere in the memory system dealing with the exclusiveness.
Some DDR controllers implement a monitor, some don't, so if non-cacheable exclusives 'work' or not is a system level thing.
Thanks for 42Bastian Schick's and Peter Rielly's explainations.
It seems my A53 system does not support exclusiveness in non-cached memory.
Is there any method to verify cache's correctness and stability?