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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 746 Questions
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  • Not Answered

    I am a little confused on this website. If I am using the amba4 protocol, which document should I read? 0

    • AMBA
    • AXI4
    1849 views
    3 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Cortex M85 Fast Model / TXEV & RXEV signals 0

    1924 views
    1 reply
    Latest over 1 year ago
    by Toshihisa Oishi Arm Employee Badge
  • Not Answered

    Coresight STM500 Required Address Space to support channel ID 0

    • Cortex-A53
    • System Guidance
    • Cortex-A
    • Debugging
    • CoreSight
    653 views
    0 replies
    Started over 1 year ago
    by Daehwan Kim
  • Not Answered

    RF45SOI GPIO information 0

    • 45RF
    573 views
    0 replies
    Started over 1 year ago
    by PETER CHENG
  • Answered

    AXI4 transaction 0

    9173 views
    19 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    CHI.F document typo issue in Table B4.14 0

    • AMBA
    • AMBA 5 CHI
    1327 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Question in CHI spec B2.7.7 Mismatched Memory attributes 0

    • CHI
    1908 views
    2 replies
    Latest over 1 year ago
    by Tony Ho
  • Not Answered

    About the size of CMN600/CMN700 SF 0

    • AMBA
    • SoC Designer
    • AMBA 5 CHI
    • Cache Coherent Interconnect
    • Bus Architecture
    680 views
    0 replies
    Started over 1 year ago
    by WhiteStone
  • Answered

    AXI4 transaction to different data width slave +1

    • APB
    • AXI
    • AXI4
    2563 views
    2 replies
    Latest over 1 year ago
    by satya vardhan
  • Answered

    AHB2AHB Bridge verification 0

    • AMBA
    • AHB2AHB
    • AHB2APB
    • AHB5
    • AHB
    1595 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    burst length of AXI. 0

    5067 views
    7 replies
    Latest over 1 year ago
    by Paul Welch
  • Suggested Answer

    fopen fails with absolute path in linux host (ubuntu 20.04) 0

    • Arm Development Studio
    • model
    • Embedded
    • Fast Models
    • ubuntu
    • Baremetal
    4115 views
    7 replies
    Latest over 1 year ago
    by Toshihisa Oishi Arm Employee Badge
  • Not Answered

    troubleshooting nIRQ Output and Address Configuration Issues with GICD_ISENABLER in ARM GIC400 0

    • GICv2
    823 views
    0 replies
    Started over 1 year ago
    by ele
  • Answered

    How to associate PL022 on Socrates +1

    • socrates
    3385 views
    6 replies
    Latest over 1 year ago
    by Manabu Tanaka
  • Not Answered

    SSE-200 subsystem w/o TrustZone 0

    591 views
    0 replies
    Started over 1 year ago
    by Makich
  • Answered

    AHB2APB Verification 0

    • AHB2APB
    • AHB5
    • Verification
    • Bridges
    • AHB
    2522 views
    3 replies
    Latest over 1 year ago
    by santhosh kola
  • Answered

    Questions regarding AMBA AHB sampling time "IHI0033C_amba_ahb_protocol_spec" 0

    • AHB-Lite
    • AMBA AHB
    • AMBA AHB Controllers
    • AHB
    4120 views
    6 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    How correctly control the Non-Sequential Strobe of axi4? 0

    • AXI4
    2945 views
    3 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    why is final state of Readunique not fixed to UD? 0

    • CHI
    2178 views
    3 replies
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Can NONSEQ in first cycle of HRESP change to IDLE? Can that happen if NONSEQ is targeting a different peripheral? 0

    1307 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
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