AHB2AHB Bridge verification

Hi,
Currently, I am working on verification of the ahb2ahb bridge, where I encountered an issue with hwstrb.

Scenario: AHB master is of 32 data width and sending a burst incremental 4 transfers to the AHB  slave of 16 data width

                       HADDR                          HWDATA                                  HWSTRB                  HSIZE
Master side :  0x00                                103Fb578                                0001                            0

                       0x01                                00000000                                0100                            0

                       0x02                                AD9833E2                               0001                           0

                       0X03                               31888AFD                                0010                           0


Slave side :  HADDR                           HWDATA                                   HwSTRB                   HSIZE
                     0x00                                b578                                             01                             0
                     0X01                               0000                                             00                              0
                     0X02                               AD98                                            00                              0
                     0X03                               0031                                             00                              0

here, i can observe that hwdata and hwstrb are taking values according offset address like for 0x03 it was taking the 24:31 bits as valid and appending extra zeroes in the slave side ,

in the protocol it was mentioned like for narrow transfers HSIZE && HADDR will decide the active byte lanes ,
-> will it still hold for a byte-addressable memory device as a slave and I want to write into individual address location with a valid strobe , if not what would be the ideal scenario to verify this
-> Is strobe always aligned with hsize and haddr (here i was used strobe according to hsize only )


Thanks in advance .

  • The AHB5 protocol allows HWSTRB bits for inactive byte lanes to be high or low (see section 3.5.2), so all of the above input values are legal, but just not sensible !!

    HADDR/HSIZE tells you which byte lanes can contain valid data, so in your above byte wide sequence this would be...

    HADDR=0 HWSTRB=0001

    HADDR=1 HWSTRB=0010

    HADDR=2 HWSTRB=0100

    HADDR=3 HWSTRB=1000

    In the AXI protocol the requirement on byte lanes that can be asserted is much stricter in that you cannot asserted them outside the AWADDR/AWSIZE/AWBURST allowed range, but the AHB5 protocol is more lenient, allowing meaningless assertions.

    So as you have coded HWSTRB, only the first transfer contained a valid byte, hence that being the only downstream transfer seen with an HWSTRB bit asserted.