Hi, Currently, I am working on verification of the ahb2ahb bridge, where I encountered an issue with hwstrb.Scenario: AHB master is of 32 data width and sending a burst incremental 4 transfers to the AHB slave of 16 data width HADDR HWDATA HWSTRB HSIZEMaster side : 0x00 103Fb578 0001 0
0x01 00000000 0100 0
0x02 AD9833E2 0001 0
0X03 31888AFD 0010 0
Slave side : HADDR HWDATA HwSTRB HSIZE 0x00 b578 01 0 0X01 0000 00 0 0X02 AD98 00 0 0X03 0031 00 0here, i can observe that hwdata and hwstrb are taking values according offset address like for 0x03 it was taking the 24:31 bits as valid and appending extra zeroes in the slave side , in the protocol it was mentioned like for narrow transfers HSIZE && HADDR will decide the active byte lanes , -> will it still hold for a byte-addressable memory device as a slave and I want to write into individual address location with a valid strobe , if not what would be the ideal scenario to verify this -> Is strobe always aligned with hsize and haddr (here i was used strobe according to hsize only )
Thanks in advance .