Iam working on AXI-APB bridge verification which supports unaligned transfers. The AXI master which is of 32 bit data width requests as follows:-
AWADDR=0x00000002 (addr.width-32 bits)
AWSIZE=2(requesting 32 bits)
AWLEN=0(single transfer)
Scenario1:- Slave data width is 32 bits. In this case as per AXI4 protocol the write should only happen to 0x00000002 and 0x00000003 address and it will not be able to write entire 32 bits.
Scenario2 :- When slave data width is 8 bits . In this case the above transaction is actually not an unaligned transaction and write should happen to 0x00000002 ,0x00000003,0x00000004 and 0x00000005 address.
Question :- Does the initiator in general know the data width,address width,memory map(base and bound address of the slave) of slave to which its transaction corresponds to.
Thank you in advance!