Iam working on AXI-APB bridge verification which supports unaligned transfers. The AXI master which is of 32 bit data width requests as follows:-
AWADDR=0x00000002 (addr.width-32 bits)
AWSIZE=2(requesting 32 bits)
AWLEN=0(single transfer)
Scenario1:- Slave data width is 32 bits. In this case as per AXI4 protocol the write should only happen to 0x00000002 and 0x00000003 address and it will not be able to write entire 32 bits.
Scenario2 :- When slave data width is 8 bits . In this case the above transaction is actually not an unaligned transaction and write should happen to 0x00000002 ,0x00000003,0x00000004 and 0x00000005 address.
Question :- Does the initiator in general know the data width,address width,memory map(base and bound address of the slave) of slave to which its transaction corresponds to.
Thank you in advance!
I'll start with a comment on your scenario 2. As you state in scenario 1, the AXI4 transaction is only accessing 0x2 and 0x3, so the same applies in scenario 2. The width of the target is irrelevant.
Moving on to your question, I would expect in some cases the initiator will know the exact form of the target, this usually being the case when accessing peripherals or I/O devices. But for general system space the initiator won't need to know the structure of the memory and will rely on the system interconnect to ensure memory accesses are performed as required.
For the memory map, the processor HW needs to know the addresses the various system resources are located at, but this would be something that is built into the SW targeted to run on this system.
Thank you so much for the reply. This answers my question. The definition of unaligned transaction in axi hence depends upon on master data width but not on target data width.