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Question in CHI spec B2.7.7 Mismatched Memory attributes

Tony Ho

in CHI spec B2.7.7 

Org:

Must ensure a Clean line, either UC or SC, in a fully coherent cache is:
– Not made visible to a Requester using a transaction with SnpAttr = 0 to access that location, if that
location has been updated by another transaction with SnpAttr = 0 after the cache line was allocated into
the fully coherent cache.

My question is the below sentence make me confusing.

"if that location has been updated by another transaction with SnpAttr = 0 after the cache line was allocated into
the fully coherent cache."

I try to understand the sentence as below.

Step1 . the cache line was allocated into the fully coherent cache 

Step 2. location has been updated by another transaction with SnpAttr = 0

The step 2 is conflict with "Not made visible to a Requester using a transaction with SnpAttr = 0 to access that location"

I think in step 2. the fully coherent cache (SnpAttr=1, I assume it is UC or SC) should not be visible to transaction with SnpAttr = 0 and can't be modified.

does my understanding is correct?

if yes,  my suggestion is I modify as below by remove some words.

Must ensure a Clean line, either UC or SC, in a fully coherent cache is:
– Not made visible to a Requester using a transaction with SnpAttr = 0 to access that location.

Tony

Parents
  • 0 in reply to Christopher Tory

    Does below scenario is correct?

    Step 1. a Clean Line in fully coherent cache

    Step 2. A Requester named RN-F1 is allow to using a transaction WriteNoSnpFull with SnpAttr = 0 to update the cache line and make a Dirty Line, I assume the Dirty Line in move to System Level Cache (SLC).

    Step 3. A Requester RN-F2 issue ReadUnique then the Dirty Cache line is move from SLC to RN-F2. the Dirty copy of a cache line is visible to a fullty coherent Requester.

    Step 4. Requester RN-F1 is allow to using a transaction with SnpAttr = 0 to access the location, HN-F need to snoop RN-F2 to keep the visibilty of  the location for RN-F1. Visibility of the Dirty line must not be removed from the Requester using a transaction with SnpAttr = 0 to
    access that location.

    Step 5. A new Requester RN-F3 is not allow to using a transaction with SnpAttr = 0 to access the location, due to it is a Dirty line and it is not allow to visible to a new Requester using a transaction with SnpAttr = 0.

Reply
  • 0 in reply to Christopher Tory

    Does below scenario is correct?

    Step 1. a Clean Line in fully coherent cache

    Step 2. A Requester named RN-F1 is allow to using a transaction WriteNoSnpFull with SnpAttr = 0 to update the cache line and make a Dirty Line, I assume the Dirty Line in move to System Level Cache (SLC).

    Step 3. A Requester RN-F2 issue ReadUnique then the Dirty Cache line is move from SLC to RN-F2. the Dirty copy of a cache line is visible to a fullty coherent Requester.

    Step 4. Requester RN-F1 is allow to using a transaction with SnpAttr = 0 to access the location, HN-F need to snoop RN-F2 to keep the visibilty of  the location for RN-F1. Visibility of the Dirty line must not be removed from the Requester using a transaction with SnpAttr = 0 to
    access that location.

    Step 5. A new Requester RN-F3 is not allow to using a transaction with SnpAttr = 0 to access the location, due to it is a Dirty line and it is not allow to visible to a new Requester using a transaction with SnpAttr = 0.

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