troubleshooting nIRQ Output and Address Configuration Issues with GICD_ISENABLER in ARM GIC400

ele 13 hours ago

I set up the following configuration to generate IRQ/FIQ interrupts for testing the ARM GIC400.

The IRQ_NUM is 2, and the GICD base address offset is 0x1000, while the GICC offset is 0x2000.
Two IRQ signals are connected to the GIC400, and after configuring the GIC400, I want to output the nIRQ and nFIQ using these two IRQ signals.

// Initial start
// GICD_ICENABLER
address = 0x1180, wdata = 0x01; // For IRQ0
// GICD_ITARGETSR
address = 0x1800, wdata = 0x01; // For CPU0

// GICD_ICENABLER
address = 0x1180, wdata = 0x02; // For IRQ1
// GICD_ITARGETSR
address = 0x1800, wdata = 0x01; // For CPU0

// GICD_CTLR
address = 0x1000, wdata = 0x03; // EnableGrp1 | EnableGrp0
// GICC_CTLR
address = 0x2000, wdata = 0x0b; // FIQEn | EnableGrp0 | EnableGrp1
// GICC_PMR
address = 0x2000, wdata = 0xff; // Priority[7:0]

// Initial End

// IRQ test start, IRQ-Level

// GICD_ISENABLER
address = 0x1100, wdata = 0x01; // Interrupt Set-Enable Registers[31:0]
repeat (10) @(posedge clk);
IRQS[0] = 1;
repeat (10) @(posedge clk);

repeat (10) @(posedge clk);
IRQS[0] = 0;
repeat (10) @(posedge clk);

address = 0x1100, wdata = 0x02; // Interrupt Set-Enable Registers[31:0]
repeat (10) @(posedge clk);
IRQS[1] = 1;
repeat (10) @(posedge clk);

repeat (10) @(posedge clk);
IRQS[1] = 0;
repeat (10) @(posedge clk);

When running this, I can't see nFIQ being output based on the level of IRQ[0] and IRQ[1].

Now I have a question:

During the IRQ test, if I set the GICD_ISENABLER address to 0x1100 instead of 0x1104, nIRQ is not output correctly. Why is this the case? Which address is correct, and why doesn't it work?"

I came across the following

The GIC assigns interrupt ID numbers (ID0-ID1019) as follows:

Interrupt numbers ID32-ID1019 are used for SPIs.
Interrupt numbers ID0-ID31 are used for interrupts that are private to a CPU interface. These interrupts are banked in the Distributor.

A banked interrupt is one where the Distributor can have multiple interrupts with the same ID. A banked interrupt is identified uniquely by its ID number and its associated CPU interface number. Of the banked interrupt IDs: — ID0-ID15 are used for SGIs — ID16-ID31 are used for PPIs ...

Interrupt numbers ID1020-ID1023 are reserved for special purposes, see Special interrupt numbers on page 3-41.

— Reference: ARM Generic Interrupt Controller Architecture Specification

According to this explanation, SPIs seem to start from ID32. Does this mean that Interrupt Set-Enable Registers[31:0] should have started with 0x1104 not 0x1100 ?

I'm confused. There are many registers in the GIC400. Do I need to pre-calculate the register addresses for ID0 to ID31, corresponding to SGI and PPI, in order to access all of these registers? For example, for registers with names ending in 'n', such as xxxxxxn, do I need to add 0x04 to the address to access them? What if I’m accessing an SPI register?