Hi All,
In APB, There are two phases. SETUP and ACCESS. The ACCESS phase is indicated by assertion of PENABLE signal. My question is why we require this phases ??
The signal PENABLE can be driven high at the same time when data and control signals are driven by master and the slave can assert the PREADY when it detects PSEL and PENABLE.
Why there is delay between assertion of PENABLE and Data/Control signals ?? Is there any reason for this delay ??