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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Answered

    Does tlm_quantumkeeper::set_global_quantum affect Fast Models? 0

    3055 views
    2 replies
    Latest over 3 years ago
    by Oscar Huang
  • Not Answered

    Model for GIC-625 0

    1024 views
    0 replies
    Started over 3 years ago
    by Oscar Huang
  • Not Answered

    Using Tmax Tetramax models for memories for scan vector generation. 0

    3106 views
    2 replies
    Latest over 3 years ago
    by Jeff_from_Draper
  • Answered

    Is Cortex-R82 fast model available? 0

    4550 views
    3 replies
    Latest over 3 years ago
    by Daniel Owens Arm Employee Badge
  • Not Answered

    Has anyone ever generated bin file for CXDT? 0

    12089 views
    1 reply
    Latest over 3 years ago
    by ghan
  • Not Answered

    Nic-400 read and write acceptance/issue configuration in socrates 0

    • socrates
    • CoreLink NIC-400
    1775 views
    0 replies
    Started over 3 years ago
    by vrk21
  • Not Answered

    How can I fix timing violation in NIC-400 bus matrix? 0

    • CoreLink NIC-400
    • CoreLink NIC-400 Network Interconnect
    1341 views
    0 replies
    Started over 3 years ago
    by Watech2010
  • Not Answered

    Regarding USB3.X Interface in ARM based microcontrollers 0

    17953 views
    1 reply
    Latest over 3 years ago
    by mkleox
  • Answered

    Should the Data value be 0 when corresponding BE is 0 in Arm CHI E Spec? 0

    • AMBA 5 CHI
    2277 views
    1 reply
    Latest over 3 years ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    In CHI, is "Device" memory type transaction, a way, to implement narrow Read transfer's ? 0

    • AMBA 5 CHI
    • CHI
    1366 views
    0 replies
    Started over 3 years ago
    by Neel_chi
  • Not Answered

    CHI data packet values for those packets outside valid byte window in a Device memory type txn 0

    1035 views
    0 replies
    Started over 3 years ago
    by Neel_chi
  • Not Answered

    CHI Device memory type unaligned transactions when size exceeds beyond next size boundary 0

    • AMBA 5 CHI
    • CHI
    1359 views
    0 replies
    Started over 3 years ago
    by Neel_chi
  • Not Answered

    CHI data size for each packets based on data bus width's 0

    • AMBA 5 CHI
    • CHI
    1532 views
    0 replies
    Started over 3 years ago
    by Neel_chi
  • Not Answered

    How to connect Master AHB lite to AHB5 Slave 0

    2132 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    What C++ standard should be used? 0

    3081 views
    1 reply
    Latest over 3 years ago
    by Toshihisa Oishi Arm Employee Badge
  • Answered

    Difference btw AXI3 and AXI4 0

    • AMBA
    • AXI3
    • AXI4
    • Interface
    41676 views
    7 replies
    Latest over 3 years ago
    by Chris06
  • Suggested Answer

    How should AXI slave handle with illegal write strobe. 0

    2826 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Rate Limit not working on Cortex-M7 FVP MPS2 0

    • mps2
    • Cortex-M7 FVP
    2181 views
    2 replies
    Latest over 4 years ago
    by Realtime Rik
  • Suggested Answer

    AHB - continue the transfer after an error response 0

    8814 views
    5 replies
    Latest over 4 years ago
    by Steven Xu Arm Employee Badge
  • Not Answered

    How can I create realm in fvp? 0

    1098 views
    0 replies
    Started over 4 years ago
    by hxxxxx
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Topics being discussed in this forum
  • ACE
  • AEMv8 FVP
  • AHB
  • AHB5
  • AHB-Lite
  • AMBA
  • AMBA 5
  • AMBA 5 CHI
  • APB
  • Arm Development Studio
  • Armv8-M
  • AXI
  • AXI4
  • Bus Architecture
  • CHI
  • CoreLink NIC-400 Network Interconnect
  • CoreSight
  • Cortex-A
  • Cortex-M
  • DesignStart
  • Fast Models
  • Fixed Virtual Platforms (FVPs)
  • Interface
  • socrates
  • TrustZone