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Is there any cache coherence between Mail400 and CPU?

Hi all. As you know, there is cache in Mail400 and A35 seperately. Do I need to implement hardware cache coherence between them, for example, using CCI.

I am designing an SOC chip with A35 and mali400. I do not know the data those need to be exchanged between mali400 and A35. If they are just some configurations, then perhaps they can be set as non-cacheable. If they are big data, then maybe it's better to set them as cachable. If the data are set as cachable, then maybe I have to consider the coherence between the cache in mali400 and A35.