Hi,
I have a problem with the signals that i received on my slave for the PS. The problem its when I declared not cacheable the memory spaced asigned to the interfaces of the M_AXI_XX (XX its LPD or FPD depends of the core) the behavior changes.
The three write channels works at expected but when you ask for a reading the signals change.
Am example its:
memcpy(0xA0000000 , datos,8);
memcpy(datos_read,0xA0000000,8);
The axi_width its 4 bytes and the memory is aligned with 8 bytes. The core of the APU its a cortexa_53 with a bus width of 16 bytes.
On this case the values of the signals on the write channel are AWSIZE = 2 and AWLEN = 1 which its interpreted as a writing of 8 bytes and the values of the signals on the read channel are AWSIZE = 2 and AWLEN = 3 which its interpreted as a reading of 16 bytes.
When I change the axi_width to 16 bytes.
On this case the values of the signals on the write channel are AWSIZE = 4 and AWLEN = 0 which its interpreted as a writing of 16 bytes and the values of the signals on the read channel are AWSIZE = 3 and AWLEN = 0 which its interpreted as a reading of 16 bytes but in this case the Write Strobes signals are enabled with a value of FF00 therefore the reading should be 8 bytes.
If anyone has any idea what might be going on. I'd appreciate it.
PD: The AXI its declared as a full AXI transfer.
Unfortunately then I can't explain why you are seeing this behaviour on the AXI bus. A non-cacheable read shouldn't then result in a longer burst which I was guessing would be a cache line fill.
It is almost certainly something specific to this Xilinx board you are using, so you would be much more likely to get an intelligent reply if you ask on a Xilinx discussion board (as opposed to my guesses).