the system have 2 masters - M0,M1, and 2 slaves- S0, S1.M0 transmit to S0, INCR4 : NON,SEQ and then early burst termination and M1 transmit to S1 new burst.In that clock cycle what S0 expects to see (in order to know on early burst termination):1. hsel HIGH + htrans = IDLE.2. hsel LOW
The answer will depend heavily on the interconnect design, so if this is an existing interconnect you have licensed it would be best to submit a support request to that company.
If the interconnect is an Arm interconnect that you have licensed, please submit a support request on the Arm systems, saying which particular AHB interconnect it is (there are a number of them) and you will probably get a more detailed response there than you might on a public forum.
If this is just a general question, either behaviour you describe could be possible.
thanks! it's a general question for interconnect i built
In that case I'd propably expect to see behaviour 2 as behaviour 1 suggests that there is some sort of state machine in the interconnect that will generate the final IDLE transfer the target is selected for.
Finishing a sequence of transfers with a final IDLE transfer is only really a recommended behaviour for "locked" sequences, where the IDLE ensures that 2 separate "locked" bursts are not all locked together as one longer sequence, so it's not something you could rely on seeing a transfer source generating for non-locked transfers.