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early burst termination - ahb - interconnect

the system have 2 masters - M0,M1, and 2 slaves- S0, S1.
M0 transmit to S0, INCR4 : NON,SEQ and then early burst termination and M1 transmit to S1 new burst.
In that clock cycle what S0 expects to see (in order to know on early burst termination):
1. hsel HIGH + htrans = IDLE.
2. hsel LOW

Top replies

Colin Campbell over 2 years ago in reply to Itamar Yunyan +2 suggested

In that case I'd propably expect to see behaviour 2 as behaviour 1 suggests that there is some sort of state machine in the interconnect that will generate the final IDLE transfer the target is selected...
Colin Campbell over 2 years ago +1 suggested

The answer will depend heavily on the interconnect design, so if this is an existing interconnect you have licensed it would be best to submit a support request to that company. If the interconnect is...